JPS61176654U - - Google Patents
Info
- Publication number
- JPS61176654U JPS61176654U JP19851484U JP19851484U JPS61176654U JP S61176654 U JPS61176654 U JP S61176654U JP 19851484 U JP19851484 U JP 19851484U JP 19851484 U JP19851484 U JP 19851484U JP S61176654 U JPS61176654 U JP S61176654U
- Authority
- JP
- Japan
- Prior art keywords
- checking
- checking means
- external
- capacity
- rams connected
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 1
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
- Debugging And Monitoring (AREA)
Description
図面はこの考案の一実施例を示すもので、第１
図は回路構成を示すブロツク図、第２図はＲＡＭ
チエツク部の詳細な構成を示す図、第３図はオプ
シヨンＲＡＭの接続構成を示す図、第４図はオプ
シヨンＲＡＭの接続状態のチエツク動作の処理内
容を示すフローチヤート、第５図、第６図はアド
レス管理部の動作を示すもので、第５図はアドレ
スを増加してデータの読出し／書込みを行なう場
合の処理内容を示すフローチヤート、第６図はア
ドレスを減少してデータの読出し／書込みを行な
う場合の処理内容を示すフローチヤートである。
１１……キー入力部、１２……キースタート信
号発生部、１３……演算部、１４……オア回路、
１５……ＲＡＭチエツク部、１６……電源スイツ
チ、１７……ＰＯＣ信号発生部１７、１８……デ
ータバス、１９，２０，２１……オプシヨンＲＡ
Ｍ、２２……デバイスコードバス、２３……アド
レスバス、２４……アドレス管理部、２５……フ
ラグＡレジスタ、２６……フラグＢレジスタ、２
７……表示部。
The drawing shows one embodiment of this invention.
The figure is a block diagram showing the circuit configuration, and Figure 2 is the RAM.
FIG. 3 is a diagram showing the detailed configuration of the check section, FIG. 3 is a diagram showing the connection configuration of the option RAM, FIG. 4 is a flowchart showing the processing contents of the operation of checking the connection state of the option RAM, and FIGS. 5 shows the operation of the address management unit, FIG. 5 is a flowchart showing the processing contents when reading/writing data by increasing the address, and FIG. 6 is a flowchart showing the processing contents when reading/writing data by decreasing the address. 3 is a flowchart showing the processing contents when performing the above. 11... Key input section, 12... Key start signal generation section, 13... Arithmetic section, 14... OR circuit,
15...RAM check unit, 16...Power switch, 17...POC signal generation unit 17, 18...Data bus, 19, 20, 21...Option RA
M, 22...Device code bus, 23...Address bus, 24...Address management section, 25...Flag A register, 26...Flag B register, 2
7...Display section.
Claims (1)
、接続される上記外部ＲＡＭの個数をチエツクす
る個数チエツク手段と、この個数チエツク手段に
伴つて接続される上記外部ＲＡＭ個々の記憶容量
をチエツクする容量チエツク手段と、この容量チ
エツク手段及び上記個数チエツク手段のチエツク
結果に応じて上記外部ＲＡＭのデータ入出力の際
のアドレス制御を行なうアドレス管理手段とを具
備したことを特徴とする小型電子機器。 In a small electronic device with removable external RAM, a number checking means for checking the number of the external RAMs connected, and a capacity checking means for checking the storage capacity of each of the external RAMs connected together with the number checking means. and address management means for controlling addresses during data input/output of the external RAM according to the check results of the capacity checking means and the number checking means.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19851484U JPS61176654U (en) | 1984-12-26 | 1984-12-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19851484U JPS61176654U (en) | 1984-12-26 | 1984-12-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61176654U true JPS61176654U (en) | 1986-11-04 |
Family
ID=30757571
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19851484U Pending JPS61176654U (en) | 1984-12-26 | 1984-12-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61176654U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6428754A (en) * | 1987-07-24 | 1989-01-31 | Hitachi Ltd | Recognizing and controlling system for memory constitution |
-
1984
- 1984-12-26 JP JP19851484U patent/JPS61176654U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6428754A (en) * | 1987-07-24 | 1989-01-31 | Hitachi Ltd | Recognizing and controlling system for memory constitution |
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