JPS642185U - - Google Patents

Description

[Brief explanation of the drawing]

Fig. 1 is a diagram showing an embodiment of this invention, Fig. 2 is a diagram showing signals of various parts of the invention, Fig. 3 is a diagram showing a conventional signal detection device, and Fig. 4 is a diagram showing various parts of the conventional device. FIG. In the figure, 1, 2, 3, 10, 11, 12 are shift registers, 4, 5, 6 are adders, 7 is an average value calculator, 8 is a multiplier, 13 is a switching device, 14 is a switching signal generator, 9 is a comparator, and X ₀ to X ₁₀ are signals of each part. Note that the same or corresponding parts in the figures are indicated by the same reference numerals.

Claims (1)

[Scope of utility model registration request] N stages of first registers that continuously delay an input signal; a second register that delays the output of the first register by one stage; and N stages of registers that continuously delay the output of the second register. a third register; a first adder that adds N outputs of N stages of the first register; and N outputs of N stages of the third register;
a second adder that adds the outputs of the first adder and the second adder, and a third adder that adds the outputs of the first adder and the second adder; , an average value calculator that calculates the average value of input signals, a multiplier that outputs the product of the output of the average value calculator and a constant K, and a fourth register that delays the output of the multiplier by N+1 stages. a register that holds the output of the multiplier; a fifth register that delays the output of the second register by N+1 stages; a switch that switches between the output of the multiplier and the output of the fourth register; A signal detection device comprising: a switching signal generator that generates a switching destination signal of a switching device; and a comparator that compares an output of the fifth register with an output of the switching device.