JPH0224392U - - Google Patents

Info

Publication number
JPH0224392U
JPH0224392U JP10181788U JP10181788U JPH0224392U JP H0224392 U JPH0224392 U JP H0224392U JP 10181788 U JP10181788 U JP 10181788U JP 10181788 U JP10181788 U JP 10181788U JP H0224392 U JPH0224392 U JP H0224392U
Authority
JP
Japan
Prior art keywords
delay
simultaneous detection
circuit
circuits
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10181788U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP10181788U priority Critical patent/JPH0224392U/ja
Publication of JPH0224392U publication Critical patent/JPH0224392U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案の一実施例のブロツク図、第
2図は他の実施例のブロツク図、第3図は従来例
のブロツク図である。 1,2,3,4…AND回路、5,6,7,8
,9,10…遅延回路、11,12…スイツチ、
13…OR回路。
FIG. 1 is a block diagram of one embodiment of this invention, FIG. 2 is a block diagram of another embodiment, and FIG. 3 is a block diagram of a conventional example. 1, 2, 3, 4...AND circuit, 5, 6, 7, 8
, 9, 10... delay circuit, 11, 12... switch,
13...OR circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 同時に入力されたことを検出すべき2つの信号
が入力される同時検出回路と、該2つの信号の一
方を他方に対して遅延させる、遅延量の異なる2
以上の遅延回路と、これらの遅延回路にそれぞれ
組み合わされ、各遅延回路をそれぞれ経た一方の
信号と他方の信号とがそれぞれ入力される2以上
の同時検出回路とからなるコインシデンス回路。
A simultaneous detection circuit that receives two signals whose input is to be detected at the same time, and a simultaneous detection circuit that delays one of the two signals with respect to the other with a different amount of delay.
A coincidence circuit comprising the above delay circuits and two or more simultaneous detection circuits that are combined with these delay circuits and receive one signal and the other signal that have passed through each delay circuit, respectively.
JP10181788U 1988-07-30 1988-07-30 Pending JPH0224392U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10181788U JPH0224392U (en) 1988-07-30 1988-07-30

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10181788U JPH0224392U (en) 1988-07-30 1988-07-30

Publications (1)

Publication Number Publication Date
JPH0224392U true JPH0224392U (en) 1990-02-19

Family

ID=31331156

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10181788U Pending JPH0224392U (en) 1988-07-30 1988-07-30

Country Status (1)

Country Link
JP (1) JPH0224392U (en)

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