JPH0293854U - - Google Patents
Info
- Publication number
- JPH0293854U JPH0293854U JP317689U JP317689U JPH0293854U JP H0293854 U JPH0293854 U JP H0293854U JP 317689 U JP317689 U JP 317689U JP 317689 U JP317689 U JP 317689U JP H0293854 U JPH0293854 U JP H0293854U
- Authority
- JP
- Japan
- Prior art keywords
- clock
- clocks
- circuit
- clock switching
- delay
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Synchronisation In Digital Transmission Systems (AREA)
Description
第１図はこの考案の一実施例によるクロツク切
替装置を示すブロツク接続図、第２図はこの考案
の他の実施例を示すクロツク切替装置のブロツク
接続図、第３図は従来のクロツク切替装置のブロ
ツク接続図である。
１，２はクロツク断検出回路、３はクロツク切
替回路、４，５は遅延回路。なお、図中、同一符
号は同一、又は相当部分を示す。
FIG. 1 is a block connection diagram showing a clock switching device according to one embodiment of this invention, FIG. 2 is a block connection diagram of a clock switching device showing another embodiment of this invention, and FIG. 3 is a conventional clock switching device. FIG. 1 and 2 are clock disconnection detection circuits, 3 is a clock switching circuit, and 4 and 5 are delay circuits. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
ツク断検出回路と、このクロツク断検出回路によ
る検出結果に応じて、上記複数系統のクロツクの
いずれかを選択して出力するクロツク切替回路と
を備えたクロツク切替装置において、少なくとも
上記クロツクが断か否かを検出する時間分遅れて
、上記各クロツクを前記クロツク切替回路に入力
する遅延回路を設けたことを特徴とするクロツク
切替装置。 A clock disconnection detection circuit detects whether the clocks of multiple systems are disconnected, and a clock switching circuit selects and outputs one of the clocks of the plurality of systems according to the detection result of the clock disconnection detection circuit. 1. A clock switching device according to the present invention, further comprising a delay circuit for inputting each of the clocks to the clock switching circuit with a delay of at least a time period for detecting whether or not the clock is turned off.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP317689U JPH0293854U (en) | 1989-01-13 | 1989-01-13 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP317689U JPH0293854U (en) | 1989-01-13 | 1989-01-13 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0293854U true JPH0293854U (en) | 1990-07-25 |
Family
ID=31204577
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP317689U Pending JPH0293854U (en) | 1989-01-13 | 1989-01-13 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0293854U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008227936A (en) * | 2007-03-13 | 2008-09-25 | Nec Electronics Corp | Clock generating circuit, clock selecting circuit, and semiconductor integrated circuit |
-
1989
- 1989-01-13 JP JP317689U patent/JPH0293854U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008227936A (en) * | 2007-03-13 | 2008-09-25 | Nec Electronics Corp | Clock generating circuit, clock selecting circuit, and semiconductor integrated circuit |