JPH0280927U - - Google Patents
Info
- Publication number
- JPH0280927U JPH0280927U JP15998688U JP15998688U JPH0280927U JP H0280927 U JPH0280927 U JP H0280927U JP 15998688 U JP15998688 U JP 15998688U JP 15998688 U JP15998688 U JP 15998688U JP H0280927 U JPH0280927 U JP H0280927U
- Authority
- JP
- Japan
- Prior art keywords
- switch
- processing circuit
- identification signal
- registers
- processing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Input From Keyboards Or The Like (AREA)
- Keying Circuit Devices (AREA)
Description
第１図は本考案の多数スイツチ処理機構の一実
施例を示したもの、第２図は従来の多数スイツチ
処理機構の一実施例を示したものである。
１：スイツチ機構、２：処理回路、３：エンコ
ーダ、４：スイツチ専用処理器、５Ａ，５Ｂ：レ
ジスタ。
FIG. 1 shows an embodiment of the multiple switch processing mechanism of the present invention, and FIG. 2 shows an embodiment of the conventional multiple switch processing mechanism. 1: Switch mechanism, 2: Processing circuit, 3: Encoder, 4: Switch dedicated processor, 5A, 5B: Register.
Claims (1)
ツチ機構において選択されたスイツチに基づいた
処理を行なう処理回路から成る多数スイツチ処理
機構に於いて、上記スイツチ機構と処理回路との
間に、スイツチ専用処理器と二つのレジスタを挿
入し、該スイツチ専用処理器により、上記スイツ
チ機構に於いて或るスイツチが選択されてから所
定の時間内に外に選択されたスイツチがあるか否
かを監視して、あつた場合には上記選択されたス
イツチの識別信号と共に該選択されたスイツチの
識別信号とを上記各々のレジスタにセツトし、無
かつた場合には上記選択されたスイツチのみの識
別信号を上記何れかのレジスタにセツトし、何れ
の場合もスイツチが選択された事を示す信号を一
個だけ上記処理回路に送る事により、該各レジス
タにセツトされた信号が該処理回路に送られる様
に成した多数スイツチ処理機構。 In a switch mechanism consisting of a large number of switches, and a multiple switch processing mechanism consisting of a processing circuit that performs processing based on the switch selected in the switch mechanism, a processor dedicated to the switch and a processor dedicated to the switch are provided between the switch mechanism and the processing circuit. Two registers are inserted, and the switch-dedicated processor monitors whether or not there is another switch selected within a predetermined time after a switch is selected in the switch mechanism. If there is no identification signal of the selected switch, the identification signal of the selected switch is set in each of the registers above, and if there is no identification signal of the selected switch, the identification signal of only the selected switch is set to one of the above registers. By setting the switch in each register and sending only one signal indicating that the switch is selected to the processing circuit in each case, the signal set in each register is sent to the processing circuit. Switch processing mechanism.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15998688U JPH0280927U (en) | 1988-12-09 | 1988-12-09 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15998688U JPH0280927U (en) | 1988-12-09 | 1988-12-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0280927U true JPH0280927U (en) | 1990-06-21 |
Family
ID=31441674
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15998688U Pending JPH0280927U (en) | 1988-12-09 | 1988-12-09 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0280927U (en) |
-
1988
- 1988-12-09 JP JP15998688U patent/JPH0280927U/ja active Pending