JPH028250U - - Google Patents

Info

Publication number
JPH028250U
JPH028250U JP8543888U JP8543888U JPH028250U JP H028250 U JPH028250 U JP H028250U JP 8543888 U JP8543888 U JP 8543888U JP 8543888 U JP8543888 U JP 8543888U JP H028250 U JPH028250 U JP H028250U
Authority
JP
Japan
Prior art keywords
circuit
data
data transfer
hardware
detect
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8543888U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP8543888U priority Critical patent/JPH028250U/ja
Publication of JPH028250U publication Critical patent/JPH028250U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Dc Digital Transmission (AREA)
  • Communication Control (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図はこの考案の一実施例であるデータ転送
回路のブロツク図、第２図はこの考案の他の実施
例のデータ転送回路のブロツク図、第３図は従来
のデータ転送回路のブロツク図を示す。 図において、２はレベル変換器、４はシリアル
／パラレルまたはパラレル／シリアル変換器、６
はＣＰＵ、７はワンシヨツト回路を示す。なお、
図中、同一符号は同一、または相当部分を示す。 Fig. 1 is a block diagram of a data transfer circuit according to one embodiment of this invention, Fig. 2 is a block diagram of a data transfer circuit according to another embodiment of this invention, and Fig. 3 is a block diagram of a conventional data transfer circuit. shows. In the figure, 2 is a level converter, 4 is a serial/parallel or parallel/serial converter, and 6 is a level converter.
7 indicates a CPU, and 7 indicates a one-shot circuit. In addition,
In the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 調歩同期式シリアル受信回路にてデータ回路に
ワンシヨツト回路を設けることにより、データブ
ロツクの終了をハードウエアにて検出することを
特徴とするデータ転送回路。 A data transfer circuit characterized in that a one-shot circuit is provided in the data circuit in an asynchronous serial receiving circuit to detect the end of a data block using hardware.
JP8543888U 1988-06-27 1988-06-27 Pending JPH028250U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8543888U JPH028250U (en) 1988-06-27 1988-06-27

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8543888U JPH028250U (en) 1988-06-27 1988-06-27

Publications (1)

Publication Number Publication Date
JPH028250U true JPH028250U (en) 1990-01-19

Family

ID=31310108

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8543888U Pending JPH028250U (en) 1988-06-27 1988-06-27

Country Status (1)

Country Link
JP (1) JPH028250U (en)

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