JPS62184476U - - Google Patents

Info

Publication number
JPS62184476U
JPS62184476U JP7133186U JP7133186U JPS62184476U JP S62184476 U JPS62184476 U JP S62184476U JP 7133186 U JP7133186 U JP 7133186U JP 7133186 U JP7133186 U JP 7133186U JP S62184476 U JPS62184476 U JP S62184476U
Authority
JP
Japan
Prior art keywords
register
selector
clock
interest
outputs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7133186U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP7133186U priority Critical patent/JPS62184476U/ja
Publication of JPS62184476U publication Critical patent/JPS62184476U/ja
Pending legal-status Critical Current

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  • Radar Systems Or Details Thereof (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来から用いられている目標検出装置
の一例を示す図、第2図はこの考案による目標検
出装置の構成図である。 図中、1はシフトレジスタ、2は加算器、3は
セレクタ、4は比較回路、5は比較回路、6はシ
フトレジスタ、7は加算器、8はセレクタ、9は
比較回路、10はコンピユータ、11はレジスタ
、12は比較回路である。なお、図中同一あるい
は相当部分には同一符号を付して示してある。
FIG. 1 is a diagram showing an example of a conventionally used target detection device, and FIG. 2 is a block diagram of a target detection device according to this invention. In the figure, 1 is a shift register, 2 is an adder, 3 is a selector, 4 is a comparison circuit, 5 is a comparison circuit, 6 is a shift register, 7 is an adder, 8 is a selector, 9 is a comparison circuit, 10 is a computer, 11 is a register, and 12 is a comparison circuit. It should be noted that the same or corresponding parts in the drawings are designated by the same reference numerals.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] レーダの受信ビデオを1クロツクごとにメモリ
していくシフトレジスタと、このシフトレジスタ
の内容を1クロツクごとに和をとり平均する加算
器と、注目するレジスタの前後の2つの加算器出
力を比較し、大きな値をとり出力するセレクタと
、前記セレクタの出力に加わえる係数をたくわえ
ておくレジスタと、注目するレジスタの内容と前
記出力との比較をとる比較回路とを備えた目標検
出装置。
A shift register that stores the radar's received video every clock, an adder that sums and averages the contents of this shift register every clock, and a comparison between the outputs of the two adders before and after the register of interest. , a selector that takes and outputs a large value, a register that stores a coefficient to be added to the output of the selector, and a comparison circuit that compares the contents of the register of interest with the output.
JP7133186U 1986-05-14 1986-05-14 Pending JPS62184476U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7133186U JPS62184476U (en) 1986-05-14 1986-05-14

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7133186U JPS62184476U (en) 1986-05-14 1986-05-14

Publications (1)

Publication Number Publication Date
JPS62184476U true JPS62184476U (en) 1987-11-24

Family

ID=30913787

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7133186U Pending JPS62184476U (en) 1986-05-14 1986-05-14

Country Status (1)

Country Link
JP (1) JPS62184476U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60151570A (en) * 1984-01-18 1985-08-09 Mitsubishi Electric Corp Signal detector

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60151570A (en) * 1984-01-18 1985-08-09 Mitsubishi Electric Corp Signal detector

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