JPS63200782U

JPS63200782U -

Info

Publication number: JPS63200782U
Application number: JP9218387U
Authority: JP
Priority date: 1987-06-16
Filing date: 1987-06-16
Publication date: 1988-12-23

Description

[Brief explanation of the drawing]

第１図は、この考案の一実施例を示す図、第２
図は本考案の各部の信号を示す図、第３図は従来
の信号検出装置を示す図、第４図は従来の装置の
各部の信号を示す図である。図中１，２，３，１０，１１，１２はレジスタ
、４，５，６は加算器、７は平均値算出器、８は
乗算器、１３は切換器、１４は切換信号発生器、
９は比較器、Ｘ_０〜Ｘ_１０は各部の信号である。
尚、図中、同一あるいは相当部分には同一符号を
示してある。 Figure 1 is a diagram showing one embodiment of this invention, Figure 2
3 is a diagram showing signals of each part of the present invention, FIG. 3 is a diagram showing a conventional signal detection device, and FIG. 4 is a diagram showing signals of each part of the conventional device. In the figure, 1, 2, 3, 10, 11, 12 are registers, 4, 5, 6 are adders, 7 is an average value calculator, 8 is a multiplier, 13 is a switch, 14 is a switching signal generator,
9 is a comparator, and X ₀ to X ₁₀ are signals of each part.
In the drawings, the same or corresponding parts are denoted by the same reference numerals.

Claims

[Scope of utility model registration request]

a first register of N stages that continuously delays an input signal; a second register that delays the output of the second register by one stage; and a second register that continuously delays the output of the second register. a third register of N stages; a first adder that adds N outputs of the N stages of the first register; and a second adder that adds N outputs of the N stages of the third register. an adder, a third adder that adds the output of the first adder and the output of the second adder, and the output of the third adder to calculate the average value of the input signal. an average value calculator for calculating the average value calculator, a multiplier for outputting the product of the output of the average value calculator and a constant K, and an output of the multiplier for N
a fourth register that delays the output of the fourth register by N+1 stages; a sixth register that delays the output of the second register by N+1 stages; and the multiplier. output, the fourth
a switch that switches the output of the register, a switch that switches the output of the fifth register, a switch signal generator that generates a switching signal for the switch, an output of the switch, and an output of the sixth register. 1. A signal detection device characterized by comprising a comparator.