JPH03107829U - - Google Patents
Info
- Publication number
- JPH03107829U JPH03107829U JP10676990U JP10676990U JPH03107829U JP H03107829 U JPH03107829 U JP H03107829U JP 10676990 U JP10676990 U JP 10676990U JP 10676990 U JP10676990 U JP 10676990U JP H03107829 U JPH03107829 U JP H03107829U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- data
- sign
- digital data
- analog signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Analogue/Digital Conversion (AREA)
Description
第１図は本考案の一実施例を示したブロツク図
、第２図および第３図は第１図の動作説明のため
の説明図、第４図は従来例を示したブロツク図、
第５図および第６図は第４図の動作説明のための
説明図である。
ＶＴ……符号反転回路、ＣＡ……加算回路、Ｒ
Ｄ……ランダムデータ発生回路、ＤＴ……Ｄ／Ａ
変換回路、ＲＥ……減算回路。
FIG. 1 is a block diagram showing an embodiment of the present invention, FIGS. 2 and 3 are explanatory diagrams for explaining the operation of FIG. 1, and FIG. 4 is a block diagram showing a conventional example.
5 and 6 are explanatory diagrams for explaining the operation of FIG. 4. VT... Sign inversion circuit, CA... Addition circuit, R
D...Random data generation circuit, DT...D/A
Conversion circuit, RE...subtraction circuit.
Claims (1)
を反転する反転回路と、上記デジタルデータｄお
よびその符号反転データを交互に選択して出力
する選択回路と、上記デジタルデータｄおよびそ
の符号反転データの供給に同期してランダムデ
ータを発生するランダムデータ発生回路と、上記
選択回路から順次供給される上記デジタルデータ
ｄおよびこのデジタルデータの符号反転データ
に対して共通のランダムデータを加算する加算回
路と、この加算回路からの出力をアナログ信号に
変換するＤ／Ａ変換回路と、このＤ／Ａ変換回路
から生じる上記デジタルデータｄに対応したアナ
ログ信号と上記符号反転データに対応したアナ
ログ信号との差をとる減算回路とからなるＤ／Ａ
変換装置。 an inversion circuit that inverts the sign of digital data d supplied at a constant cycle; a selection circuit that alternately selects and outputs the digital data d and its sign-inverted data; and a supply of the digital data d and its sign-inverted data. a random data generation circuit that generates random data in synchronization with the selection circuit; an addition circuit that adds common random data to the digital data d sequentially supplied from the selection circuit and sign-inverted data of the digital data; A D/A conversion circuit that converts the output from the adder circuit into an analog signal, and the difference between the analog signal corresponding to the digital data d generated from this D/A conversion circuit and the analog signal corresponding to the sign-inverted data is calculated. D/A consisting of a subtraction circuit
conversion device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10676990U JPH03107829U (en) | 1990-10-11 | 1990-10-11 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10676990U JPH03107829U (en) | 1990-10-11 | 1990-10-11 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03107829U true JPH03107829U (en) | 1991-11-06 |
Family
ID=31655493
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10676990U Pending JPH03107829U (en) | 1990-10-11 | 1990-10-11 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03107829U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60128719A (en) * | 1983-12-16 | 1985-07-09 | Toshiba Corp | Digital-analog converter |
| JPS61121532A (en) * | 1984-11-17 | 1986-06-09 | Sony Corp | Deglitch circuit |
-
1990
- 1990-10-11 JP JP10676990U patent/JPH03107829U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60128719A (en) * | 1983-12-16 | 1985-07-09 | Toshiba Corp | Digital-analog converter |
| JPS61121532A (en) * | 1984-11-17 | 1986-06-09 | Sony Corp | Deglitch circuit |