JPH0478864U - - Google Patents

Description

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a video signal digital conversion circuit according to an embodiment of this invention, and FIG.
3 is a clamp circuit diagram of a conventional circuit; FIG. 4 is a waveform diagram of a video input signal to explain the operation of the conventional circuit;
Fig. 5 is an explanatory diagram showing the synchronization detection operation of the clamp circuit, Fig. 6 is a circuit diagram of a conventional AD converter, Fig. 7 is an explanatory diagram showing the operation of Figs. 8 and 6, Fig. 8 1 is a reference voltage generation circuit diagram using a conventional circuit system. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Scope of utility model registration request] A video amplifier that generates an appropriate signal to the AD converter, an AD converter that converts an analog signal to a digital signal, a register that holds digital data corresponding to the pedestal level of the video signal, and the conversion data and pedestal value of the AD converter. A subtracter and AD that performs subtraction with a holding register
A video signal-to-digital conversion circuit is comprised of a reference voltage generator that generates a reference voltage to a converter, and is characterized by realizing a conventional analog pedestal clamp circuit in a digital manner.