JPS6444439U - - Google Patents

Info

Publication number
JPS6444439U
JPS6444439U JP14050387U JP14050387U JPS6444439U JP S6444439 U JPS6444439 U JP S6444439U JP 14050387 U JP14050387 U JP 14050387U JP 14050387 U JP14050387 U JP 14050387U JP S6444439 U JPS6444439 U JP S6444439U
Authority
JP
Japan
Prior art keywords
reverberation
output
adding means
delay
outputs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14050387U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP14050387U priority Critical patent/JPS6444439U/ja
Publication of JPS6444439U publication Critical patent/JPS6444439U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例に係る残響付加装置
の原理ブロツク図、第2図は本考案の一実施例に
係る残響付加装置の具体的構成を示すブロツク図
、第3図a,bは第2図の音色パラメータメモリ
35の内聞構成を示す図、第4図a,bは第2図
の音色パラメータメモリ36の内部構成を示す図
、第5図は第2図の波形データメモリの内部構成
を示す図、第6図は残響付加装置の処理動作を示
す図である。 11……残響付加回路、12……初期反射付加
回路、13−1〜13−7……遅延回路、14−
1〜14−6……乗算器、15−1〜15−6…
…加算器、17,18,22……乗算器、19,
20,21,23,24……加算器、31……プ
ログラムメモリ、35,36……音色パラメータ
メモリ、39……演算回路、40……乗算回路、
43……波形データメモリ。
FIG. 1 is a principle block diagram of a reverberation adding device according to an embodiment of the present invention, FIG. 2 is a block diagram showing a specific configuration of a reverberation adding device according to an embodiment of the present invention, and FIGS. 3 a and b 2 shows the internal configuration of the timbre parameter memory 35 in FIG. 2, FIGS. 4a and 4b show the internal configuration of the timbre parameter memory 36 in FIG. 2, and FIG. 5 shows the internal configuration of the timbre parameter memory 36 in FIG. 2. FIG. 6 is a diagram showing the processing operation of the reverberation adding device. 11...Reverberation addition circuit, 12...Early reflection addition circuit, 13-1 to 13-7...Delay circuit, 14-
1 to 14-6...multiplier, 15-1 to 15-6...
... Adder, 17, 18, 22 ... Multiplier, 19,
20, 21, 23, 24... Adder, 31... Program memory, 35, 36... Tone parameter memory, 39... Arithmetic circuit, 40... Multiplication circuit,
43... Waveform data memory.

Claims (1)

【実用新案登録請求の範囲】 (1) 入力信号に対し複数の遅延時間出力を得る
遅延手段よりなる初期反射付加手段と、 該初期反射付加手段の出力を入力とする複数の
遅延手段よりなる残響付加手段と、 前記初期反射付加手段及び残響付加手段の出力
音量をそれぞれ調整する音量調整手段と、 前記音量調整手段の出力を加算する加算手段と
を有することを特徴とする残響付加装置。 (2) 前記残響付加手段は、前記初期反射付加手
段の出力を共通に受ける複数の遅延手段よりなる
入力側残響付加手段と、該入力側残響付加手段の
出力を共通の入力とする2組の遅延手段と、前記
2組の遅延手段の出力を各々独立して出力する出
力手段とを有し、前記出力手段よりステレオ出力
を得ることを特徴とする実用新案登録請求の範囲
第1項記載の残響付加装置。
[Claims for Utility Model Registration] (1) Early reflection adding means consisting of a delay means that obtains a plurality of delay time outputs for an input signal, and reverberation consisting of a plurality of delay means whose inputs are the outputs of the early reflection adding means. A reverberation adding device comprising: an adding means; a sound volume adjusting means for adjusting the output volumes of the early reflection adding means and the reverberation adding means; and an adding means for adding the outputs of the sound volume adjusting means. (2) The reverberation adding means includes an input side reverberation adding means consisting of a plurality of delay means that commonly receives the output of the early reflection adding means, and two sets of input side reverberation adding means having the output of the input side reverberation adding means as a common input. A utility model according to claim 1, comprising a delay means and an output means for independently outputting the outputs of the two sets of delay means, and a stereo output is obtained from the output means. Reverberation adding device.
JP14050387U 1987-09-14 1987-09-14 Pending JPS6444439U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14050387U JPS6444439U (en) 1987-09-14 1987-09-14

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14050387U JPS6444439U (en) 1987-09-14 1987-09-14

Publications (1)

Publication Number Publication Date
JPS6444439U true JPS6444439U (en) 1989-03-16

Family

ID=31404733

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14050387U Pending JPS6444439U (en) 1987-09-14 1987-09-14

Country Status (1)

Country Link
JP (1) JPS6444439U (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5642292A (en) * 1979-09-14 1981-04-20 Nippon Musical Instruments Mfg Sound effect device
JPS5821299A (en) * 1981-07-30 1983-02-08 ヤマハ株式会社 Reverberation sound adding apparatus
JPS58205195A (en) * 1982-05-26 1983-11-30 松下電器産業株式会社 Reverberation apparatus

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5642292A (en) * 1979-09-14 1981-04-20 Nippon Musical Instruments Mfg Sound effect device
JPS5821299A (en) * 1981-07-30 1983-02-08 ヤマハ株式会社 Reverberation sound adding apparatus
JPS58205195A (en) * 1982-05-26 1983-11-30 松下電器産業株式会社 Reverberation apparatus

Similar Documents

Publication Publication Date Title
JPS6444439U (en)
JPS6432599U (en)
JPS62155880A (en) Personal computer
JPS6432600U (en)
JPH0423280Y2 (en)
JPS6119298U (en) delay device
JPH02187797A (en) Electronic musical instrument
JPS6199198U (en)
JPH06130942A (en) Acoustic effect device
JPH0390300U (en)
JPS62129894A (en) Waveform generator
JPS59164096U (en) electronic sound device
JPS6432597U (en)
JPH0221866U (en)
JPS63263899A (en) Input device for sound field control device
JPS59168798U (en) audio tone effect device
JPS5871796U (en) Ensemble circuit for electronic musical instruments
JPS63114591U (en)
JPS61189700U (en)
JPH0370655U (en)
JPH0377998U (en)
JPS6364096A (en) Echo sound generator
JPS5917468U (en) Pitch evaluation device
JPS6168298U (en)
JPS6031691U (en) clock device