JPS6432597U - - Google Patents

Info

Publication number
JPS6432597U
JPS6432597U JP12680287U JP12680287U JPS6432597U JP S6432597 U JPS6432597 U JP S6432597U JP 12680287 U JP12680287 U JP 12680287U JP 12680287 U JP12680287 U JP 12680287U JP S6432597 U JPS6432597 U JP S6432597U
Authority
JP
Japan
Prior art keywords
effect adding
adding means
effect
input signal
digital
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12680287U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP12680287U priority Critical patent/JPS6432597U/ja
Publication of JPS6432597U publication Critical patent/JPS6432597U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の原理を示す効果付加装置の回
路ブロツク図、第2図は第1図のデイレイ効果付
加回路の一例を示すブロツク図、第3図は第1図
のコーラス効果付加回路の一例を示す図、第4図
は第1図のリバーブ効果付加回路の一例を示すブ
ロツク図、第5図は本考案の一実施例に係る効果
付加装置の具体的構成を示すブロツク図、第6図
は第5図の音色パラメータメモリ35の内部構成
を示す図、第7図は第5図の音色パラメータメモ
リ36の内部構成を示す図、第8図は同実施例の
効果付加装置の全体の処理動作を示すフローチヤ
ート、第9図は第8図のデイレイ効果付加の処理
動作を示すフローチヤート、第10図は第8図の
コーラス効果付加の処理動作を示すフローチヤー
ト、第11図は第8図のリバーブ効果付加の処理
動作を示すフローチヤート、第12図はリバーブ
効果の演算処理を説明する図、第13図は従来の
効果付加装置の原理ブロツク図である。 11……デイレイ効果付加回路、12……コー
ラス効果付加回路、13……リバーブ効果付加回
路、14,18……加算器、15,17,20,
21……D/A変換器、16,19……乗算器、
22……アナログ加算器、31……プログラムメ
モリ、35,36……音色パラメータメモリ、3
9……演算回路、40……乗算回路、43……波
形データメモリ、55……D/A変換器、61…
…アナログ加算器。
Fig. 1 is a circuit block diagram of an effect adding device showing the principle of the present invention, Fig. 2 is a block diagram showing an example of the delay effect adding circuit of Fig. 1, and Fig. 3 is a circuit diagram of the chorus effect adding circuit of Fig. 1. 4 is a block diagram showing an example of the reverb effect adding circuit of FIG. 1, FIG. 5 is a block diagram showing a specific configuration of an effect adding device according to an embodiment of the present invention, and FIG. This figure shows the internal structure of the tone parameter memory 35 in FIG. 5, FIG. 7 shows the internal structure of the tone parameter memory 36 in FIG. 5, and FIG. 8 shows the entire effect adding device of the same embodiment. FIG. 9 is a flowchart showing the processing operation for adding the delay effect in FIG. 8. FIG. 10 is a flowchart showing the processing operation for adding the chorus effect in FIG. 8. FIG. 8 is a flowchart showing the processing operation for adding the reverb effect, FIG. 12 is a diagram explaining the calculation process for the reverb effect, and FIG. 13 is a principle block diagram of a conventional effect adding device. 11... Delay effect adding circuit, 12... Chorus effect adding circuit, 13... Reverb effect adding circuit, 14, 18... Adder, 15, 17, 20,
21... D/A converter, 16, 19... Multiplier,
22...Analog adder, 31...Program memory, 35, 36...Tone parameter memory, 3
9... Arithmetic circuit, 40... Multiplication circuit, 43... Waveform data memory, 55... D/A converter, 61...
...Analog adder.

Claims (1)

【実用新案登録請求の範囲】 (1) デジタル入力信号に種々の効果を付加して
出力する複数接続された効果付加手段と、 前記デジタル入力信号及び各効果付加手段の出
力信号をそれぞれデジタル信号からアナログ信号
に変換するデジタル・アナログ変換手段と、 前記デジタル・アナログ変換手段の各アナログ
信号出力を加算するアナログ加算手段と、 を有することを特徴とする効果付加装置。 (2) 前記複数接続された効果付加手段は、入力
信号に効果を付加する前段の効果付加手段と、該
前段の効果付加手段の出力信号と入力信号との加
算値を入力信号とする後段の効果付加手段とを有
することを特徴とする実用新案登録請求の範囲第
1項記載の効果付加装置。 (3) 前記複数接続された効果付加手段は、デイ
レイ効果付加手段と、コーラス効果付加手段と、
リバーブ効果付加手段との少なくとも2つを有す
ることを特徴とする実用新案登録請求の範囲第1
項または第2項のいずれかに記載の効果付加装置
[Claims for Utility Model Registration] (1) A plurality of connected effect adding means for adding and outputting various effects to a digital input signal, and converting the digital input signal and the output signal of each effect adding means from a digital signal, respectively. An effect adding device comprising: digital-to-analog conversion means for converting into an analog signal; and analog addition means for adding up respective analog signal outputs of the digital-to-analog conversion means. (2) The plurality of connected effect adding means includes a former effect adding means that adds an effect to an input signal, and a latter effect adding means that uses the sum of the output signal of the preceding effect adding means and the input signal as an input signal. 2. The effect adding device according to claim 1, further comprising an effect adding means. (3) The plurality of connected effect adding means includes a delay effect adding means, a chorus effect adding means,
Utility model registration claim 1 characterized by having at least two reverb effect adding means
2. The effect adding device according to claim 1 or 2.
JP12680287U 1987-08-20 1987-08-20 Pending JPS6432597U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12680287U JPS6432597U (en) 1987-08-20 1987-08-20

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12680287U JPS6432597U (en) 1987-08-20 1987-08-20

Publications (1)

Publication Number Publication Date
JPS6432597U true JPS6432597U (en) 1989-03-01

Family

ID=31378650

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12680287U Pending JPS6432597U (en) 1987-08-20 1987-08-20

Country Status (1)

Country Link
JP (1) JPS6432597U (en)

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