JPS6296758U - - Google Patents

Info

Publication number
JPS6296758U
JPS6296758U JP19003485U JP19003485U JPS6296758U JP S6296758 U JPS6296758 U JP S6296758U JP 19003485 U JP19003485 U JP 19003485U JP 19003485 U JP19003485 U JP 19003485U JP S6296758 U JPS6296758 U JP S6296758U
Authority
JP
Japan
Prior art keywords
data
analog
outputs
digital data
weighting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19003485U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP19003485U priority Critical patent/JPS6296758U/ja
Publication of JPS6296758U publication Critical patent/JPS6296758U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Complex Calculations (AREA)
  • Apparatus For Radiation Diagnosis (AREA)
  • Picture Signal Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

図は本考案の一実施例である積和演算回路を示
す。 1……画像演算回路、2……デジタルデータの
入力手段、3……重み付け用データの発生器、4
……アナログ出力型の乗算器、5……アナログ加
算器、6……D/Aコンバータのアレイ、7……
乗算型D/Aコンバータ。
The figure shows a product-sum calculation circuit which is an embodiment of the present invention. 1... Image calculation circuit, 2... Digital data input means, 3... Weighting data generator, 4
...analog output type multiplier, 5...analog adder, 6...D/A converter array, 7...
Multiplying D/A converter.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] n個のデジタルデータの入力手段と、このデー
タ各々についてのn個の重み付けデータの発生器
と、上記デジタルデータの各々について上記重み
付けデータによる積算をし、その結果であるn個
の積をアナログ量で出力する乗算器と、上記n個
のアナログ出力を加算するアナログ加算器とを具
備したことを特徴とする画像演算回路。
An input means for n digital data, a generator for n weighting data for each of the data, and integrating each of the digital data using the weighting data, and converting the resulting n product into an analog quantity. 1. An image calculation circuit comprising: a multiplier that outputs an output signal; and an analog adder that adds the n analog outputs.
JP19003485U 1985-12-09 1985-12-09 Pending JPS6296758U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19003485U JPS6296758U (en) 1985-12-09 1985-12-09

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19003485U JPS6296758U (en) 1985-12-09 1985-12-09

Publications (1)

Publication Number Publication Date
JPS6296758U true JPS6296758U (en) 1987-06-20

Family

ID=31142876

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19003485U Pending JPS6296758U (en) 1985-12-09 1985-12-09

Country Status (1)

Country Link
JP (1) JPS6296758U (en)

Similar Documents

Publication Publication Date Title
JPS6296758U (en)
JPS6160340U (en)
JPS6355180U (en)
JPS6432597U (en)
JPS6269169U (en)
JPH0299368U (en)
JPH0195875U (en)
JPS5899931U (en) Digital-to-analog conversion circuit
JPS61158744U (en)
JPH0174637U (en)
JPH0232244U (en)
JPH0245480U (en)
JPS6341936U (en)
JPS61187131U (en)
JPS6392950U (en)
JPS6392439U (en)
JPS63163536U (en)
JPH02118374U (en)
JPH0434009U (en)
JPS625934U (en)
JPH0452244U (en)
JPH03100942U (en)
JPH0397239U (en)
JPS63140737U (en)
JPS63118644U (en)