JPH0232244U - - Google Patents
Info
- Publication number
- JPH0232244U JPH0232244U JP11135588U JP11135588U JPH0232244U JP H0232244 U JPH0232244 U JP H0232244U JP 11135588 U JP11135588 U JP 11135588U JP 11135588 U JP11135588 U JP 11135588U JP H0232244 U JPH0232244 U JP H0232244U
- Authority
- JP
- Japan
- Prior art keywords
- converter
- delay time
- delay circuit
- adder
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Analogue/Digital Conversion (AREA)
Description
第１図は本考案の一実施例の回路図である。
１……デイジタル入力データ、２……クロツク
、３……デイジタル入力回路、４……デコーダ、
５，６……遅延回路、７……上位データ変換用Ｄ
／Ａ変換器、８……下位データ変換用Ｄ／Ａ変換
器、９……ボルテージフオロワ、１０……加算器
、Ｒ１……加算抵抗１、Ｒ２……加算抵抗２。
FIG. 1 is a circuit diagram of an embodiment of the present invention. 1...Digital input data, 2...Clock, 3...Digital input circuit, 4...Decoder,
5, 6...Delay circuit, 7...D for upper data conversion
/A converter, 8... D/A converter for lower data conversion, 9... Voltage follower, 10... Adder, R1... Addition resistor 1, R2... Addition resistor 2.
Claims (1)
よび下位側データをそれぞれ変換する第１および
第２のＤ／Ａ変換器と、これら第１および第２の
Ｄ／Ａ変換器の出力信号を加算する加算器とを有
するＤ／Ａ変換器において、前記第１のＤ／Ａ変
換器の入力側に第１の遅延回路をもうけ、前記第
２のＤ／Ａ変換器の入力側に第２の遅延回路をも
うけ、前記第１の遅延回路の遅延時間と前記第２
の遅延回路の遅延時間とを、前記第１のＤ／Ａ変
換器の出力から前記加算器の入力までの伝播遅延
時間と前記第２のＤ／Ａ変換器の出力から前記加
算器の入力までの伝播遅延時間とが等しくなるよ
うに設定したことを特徴とするＤ／Ａ変換器。 First and second D/A converters that convert upper and lower data of digital data to be converted, respectively; and an adder that adds output signals of these first and second D/A converters. In the D/A converter, a first delay circuit is provided on the input side of the first D/A converter, and a second delay circuit is provided on the input side of the second D/A converter. and the delay time of the first delay circuit and the second delay circuit.
The delay time of the delay circuit is defined as the propagation delay time from the output of the first D/A converter to the input of the adder, and the propagation delay time from the output of the second D/A converter to the input of the adder. A D/A converter characterized in that the propagation delay time of the D/A converter is set to be equal to the propagation delay time of the D/A converter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11135588U JPH0232244U (en) | 1988-08-24 | 1988-08-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11135588U JPH0232244U (en) | 1988-08-24 | 1988-08-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0232244U true JPH0232244U (en) | 1990-02-28 |
Family
ID=31349325
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11135588U Pending JPH0232244U (en) | 1988-08-24 | 1988-08-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0232244U (en) |
-
1988
- 1988-08-24 JP JP11135588U patent/JPH0232244U/ja active Pending
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