JPH0288328U

JPH0288328U -

Info

Publication number: JPH0288328U
Application number: JP16785388U
Authority: JP
Priority date: 1988-12-26
Filing date: 1988-12-26
Publication date: 1990-07-12

Description

[Brief explanation of the drawing]

第１図はこの考案による実施例の構成図、第２
図は第１図のタイムチヤート、第３図は従来技術
の構成図、第４図は第３図のタイムチヤートであ
る。１……セレクタ、１Ａ……第１の端子、１Ｂ…
…第２の端子、２Ａ……加算器、２Ｂ……減算器
、３……ＦＦ、４……Ｄ／Ａ変換器、１１……初
期データ、１２……セレクタ信号、１３……ステ
ツプデータ、１４……クロツク、１４Ａ……第１
番目のクロツク、１４Ｂ……第２番目のクロツク
。 Figure 1 is a configuration diagram of an embodiment according to this invention, Figure 2
The figures are the time chart of FIG. 1, FIG. 3 is a configuration diagram of the prior art, and FIG. 4 is the time chart of FIG. 3. 1... Selector, 1A... First terminal, 1B...
...Second terminal, 2A...Adder, 2B...Subtractor, 3...FF, 4...D/A converter, 11...Initial data, 12...Selector signal, 13...Step data, 14...Clock, 14A...1st
2nd clock, 14B...2nd clock.

Claims

[Claims for Utility Model Registration] 1. A selector 1 that selects a first terminal 1A input and a second terminal 1B input using a selector signal 12, an adder 2A that adds step data 13 and the output of the selector 1, and an addition. FF3 that latches the output of the converter 2A with the clock 14, and a D/A converter 4 that converts the output of FF3 to D/A.
and transmits the initial data 11 to the first terminal 1A of the selector 1.
In addition, the output of FF3 is applied to the second terminal 1B of the selector 1, and according to the selector signal 12, the initial data 11 is extracted from the output of the selector 1 at the first clock 14, and the output from the selector 1 is output at the second and subsequent clocks 14. 1, the output of the FF 3 is taken out, and a staircase wave is taken out from the output of the D/A converter 4 in steps of voltage corresponding to step data 13 at the cycle of the clock 14. 2. A selector 1 that selects the first terminal 1A input and the second terminal 1B input using the selector signal 12, a subtracter 2B that subtracts the step voltage 13 and the output of the selector 1, and a clock 14 that selects the output of the subtracter 2B. FF3 to latch and D/A converter 4 to D/A convert the output of FF3
and transmits the initial data 11 to the first terminal 1A of the selector 1.
In addition, the output of FF3 is applied to the second terminal 1B of the selector 1, and according to the selector signal 12, the initial data 11 is extracted from the output of the selector 1 at the first clock 14, and the output from the selector 1 is output at the second and subsequent clocks 14. 1, the output of FF3 is taken out, and a staircase wave is taken out from the output of D/A converter 4, which steps down by a voltage corresponding to step data 13 at the cycle of clock 14.