JPH0344934U

JPH0344934U -

Info

Publication number: JPH0344934U
Application number: JP10498289U
Authority: JP
Priority date: 1989-09-07
Filing date: 1989-09-07
Publication date: 1991-04-25

Description

[Brief explanation of the drawing]

第１図は本考案によるＳ／Ｐ変換器を示すブロ
ツク図、第２図は本考案の動作を示すタイムチイ
ヤート、第３図は従来のＳ／Ｐ変換器を示すブロ
ツク図、第４図はリングカウンタ部の動作を示す
タイムチヤートである。図において１……Ｓ／Ｐ変換器、２……パラレ
ル変換部、３……ラツチ部、４……リングカウン
タ部、５……Ｄ／Ａ変換器、６……デイレイライ
ン、７……ラツチ用クロツク制御部である。なお
、各図中、同一符号は同一または相当部分を示す
。 Fig. 1 is a block diagram showing the S/P converter according to the present invention, Fig. 2 is a time chart showing the operation of the present invention, Fig. 3 is a block diagram showing the conventional S/P converter, and Fig. 4 is a block diagram showing the S/P converter according to the present invention. The figure is a time chart showing the operation of the ring counter section. In the figure, 1...S/P converter, 2...Parallel conversion section, 3...Latch section, 4...Ring counter section, 5...D/A converter, 6...Delay line, 7...Latch This is a clock control section for use. In each figure, the same reference numerals indicate the same or corresponding parts.

Claims

[Scope of utility model registration request]

A latch section that latches and outputs the parallel data in a serial/parallel converter that inputs serial data with a transmission frequency of ₀ , converts the serial data into parallel data with a transmission frequency of ₁ , and outputs it to a digital/analog converter. Then, divide the externally inputted clock with a frequency of ₀ ,
a ring counter section that outputs a latch clock of frequency ₁ to the latch section;
The sampling clock and the latch clock of the analog converter are input, the timings of both clocks are compared, and if the timing is not within the set range, the ring counter is controlled to A serial/parallel converter comprising a latch clock control section that shifts the phase of a latch clock.