JPH0298528U - - Google Patents
Info
- Publication number
- JPH0298528U JPH0298528U JP502189U JP502189U JPH0298528U JP H0298528 U JPH0298528 U JP H0298528U JP 502189 U JP502189 U JP 502189U JP 502189 U JP502189 U JP 502189U JP H0298528 U JPH0298528 U JP H0298528U
- Authority
- JP
- Japan
- Prior art keywords
- sample
- latch
- output
- jitter
- analog
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims description 2
- 238000010521 absorption reaction Methods 0.000 claims 2
- 230000010355 oscillation Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Analogue/Digital Conversion (AREA)
Description
第1図はこの考案の一実施例の構成を示すブロ
ツク図。第2図はこの考案の一実施例の作用の説
明に供するタイミング図。第3図は従来例の構成
を示すブロツク図。第4図はD/A変換器の変換
時のタイミング図。
1……デジタルフイルタ、2……D/A変換器
、10……発振器、11……Dフリツプフロツプ
、12……デイグリツチ回路。
FIG. 1 is a block diagram showing the configuration of an embodiment of this invention. FIG. 2 is a timing diagram for explaining the operation of one embodiment of this invention. FIG. 3 is a block diagram showing the configuration of a conventional example. FIG. 4 is a timing chart during conversion of the D/A converter. 1... Digital filter, 2... D/A converter, 10... Oscillator, 11... D flip-flop, 12... Day glitch circuit.
Claims (1)
信号のジツタを吸収するジツタ吸収回路であつて
、発振器と、前記発振器に発振出力をクロツクと
してデイグリツチ信号をラツチするラツチ手段と
、前記変換アナログ信号を前記ラツチ手段からの
ラツチ出力によりサンプルホールドするサンプル
ホールド手段とを備え、前記サンプルホールド手
段の出力をアナログ変換信号とすることを特徴と
するジツタ吸収回路。 A jitter absorption circuit for absorbing jitter in an analog signal converted by a digital/analog converter, the circuit comprising: an oscillator; latch means for latching a day latch signal using the oscillation output as a clock; 1. A jitter absorption circuit, comprising: sample and hold means for holding a sample based on a latch output, and an output of said sample and hold means is used as an analog conversion signal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP502189U JPH0298528U (en) | 1989-01-21 | 1989-01-21 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP502189U JPH0298528U (en) | 1989-01-21 | 1989-01-21 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0298528U true JPH0298528U (en) | 1990-08-06 |
Family
ID=31208031
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP502189U Pending JPH0298528U (en) | 1989-01-21 | 1989-01-21 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0298528U (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5862928A (en) * | 1981-10-09 | 1983-04-14 | Matsushita Electric Ind Co Ltd | Deglitch circuit |
-
1989
- 1989-01-21 JP JP502189U patent/JPH0298528U/ja active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5862928A (en) * | 1981-10-09 | 1983-04-14 | Matsushita Electric Ind Co Ltd | Deglitch circuit |
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