JPH0338935U - - Google Patents
Info
- Publication number
- JPH0338935U JPH0338935U JP9878189U JP9878189U JPH0338935U JP H0338935 U JPH0338935 U JP H0338935U JP 9878189 U JP9878189 U JP 9878189U JP 9878189 U JP9878189 U JP 9878189U JP H0338935 U JPH0338935 U JP H0338935U
- Authority
- JP
- Japan
- Prior art keywords
- sampling clock
- adc
- output
- oscillator
- buffer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005070 sampling Methods 0.000 claims 6
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Analogue/Digital Conversion (AREA)
Description
第１図は本考案に係る多チヤンネルＡＤ変換装
置の一実施例を示す図、第２図は従来例を示す図
である。
１，１１……アンプ、２，２１……ＡＤＣ、３
，３１……ラツチ回路、４……分周器、５……発
振器、６，７，６１，７１……バツフア。
FIG. 1 is a diagram showing an embodiment of a multi-channel AD converter according to the present invention, and FIG. 2 is a diagram showing a conventional example. 1, 11...Amplifier, 2, 21...ADC, 3
, 31... Latch circuit, 4... Frequency divider, 5... Oscillator, 6, 7, 61, 71... Buffer.
Claims (1)
換器（以下、単にＡＤＣと記す）と、このＡＤＣ
にサンプリングクロツクを加える発振器と、この
サンプリングクロツクを分周する分周器と、分周
器の分周出力のタイミングでＡＤＣの出力をラツ
チするラツチ回路と、を各チヤンネル回路に備え
、 かつ、 入力端子Ｐ２に加えられたサンプリングクロツ
クを受ける第１のバツフア６と、 前記発振器のサンプリングクロツクを受けて出
力端子Ｐ３に出力する第２のバツフア７と、 前記発振器からのサンプリングクロツクと、前
記第１のバツフアの出力とを切替えて、ＡＤＣと
分周器に加えるスイツチと、 を各チヤンネル回路に備えた多チヤンネルＡＤ変
換装置。[Claims for Utility Model Registration] An AD converter (hereinafter simply referred to as ADC) that converts an analog signal into a digital signal, and this ADC
Each channel circuit is provided with an oscillator that applies a sampling clock to the sampling clock, a frequency divider that divides the frequency of this sampling clock, and a latch circuit that latches the output of the ADC at the timing of the frequency division output of the frequency divider, and , a first buffer 6 that receives the sampling clock applied to the input terminal P2, a second buffer 7 that receives the sampling clock of the oscillator and outputs it to the output terminal P3, and a sampling clock from the oscillator. , a switch for switching the output of the first buffer and applying it to an ADC and a frequency divider, and each channel circuit is provided with a switch.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9878189U JPH0338935U (en) | 1989-08-24 | 1989-08-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9878189U JPH0338935U (en) | 1989-08-24 | 1989-08-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0338935U true JPH0338935U (en) | 1991-04-15 |
Family
ID=31647865
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9878189U Pending JPH0338935U (en) | 1989-08-24 | 1989-08-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0338935U (en) |
-
1989
- 1989-08-24 JP JP9878189U patent/JPH0338935U/ja active Pending