JPH01177619U - - Google Patents
Info
- Publication number
- JPH01177619U JPH01177619U JP7426688U JP7426688U JPH01177619U JP H01177619 U JPH01177619 U JP H01177619U JP 7426688 U JP7426688 U JP 7426688U JP 7426688 U JP7426688 U JP 7426688U JP H01177619 U JPH01177619 U JP H01177619U
- Authority
- JP
- Japan
- Prior art keywords
- branch
- outputs
- output
- converter
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims 2
- 230000003111 delayed effect Effects 0.000 claims 1
- 238000005070 sampling Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
- 238000001228 spectrum Methods 0.000 description 1
Landscapes
- Analogue/Digital Conversion (AREA)
Description
第１図は本考案の一実施例の回路ブロツク図、
第２図は１例として回路の各部の波形を示す図、
第３図は復元波形の改善効果を示す図、第４図は
本実施例の補間関数を示す図、第５図は補間関数
のスペクトル図である。
１……単位遅延素子、２……減算器、１０……
第１枝路、１１……Ｄ／Ａ変換器、１２……電流
・電圧変換器、２０……第２枝路、２１……Ｄ／
Ａ変換器、２２……チヨツパ放電回路付積分器、
３０……加算器。
FIG. 1 is a circuit block diagram of an embodiment of the present invention.
FIG. 2 is a diagram showing waveforms of each part of the circuit as an example,
FIG. 3 is a diagram showing the improvement effect of the restored waveform, FIG. 4 is a diagram showing the interpolation function of this embodiment, and FIG. 5 is a spectrum diagram of the interpolation function. 1...Unit delay element, 2...Subtractor, 10...
First branch, 11...D/A converter, 12...Current/voltage converter, 20...Second branch, 21...D/
A converter, 22...Integrator with chopper discharge circuit,
30...adder.
Claims (1)
力し、Ｄ／Ａ変換器を経て、アナログ電圧として
出力する第１枝路と、入力デイジタル信号から１
単位遅延した信号を減算して得た差分信号を入力
し、Ｄ／Ａ変換器と、その出力を１サンプリング
期間積分し、該期間の始まりに放電させるチヨツ
パ放電回路付積分器とを経て、アナログ電圧とし
て出力する第２枝路と、前記第１枝路、第２枝路
の各出力を合成し、アナログ変換出力として出力
する加算器とからなることを特徴とするＤ／Ａ変
換回路。 A first branch that inputs a signal delayed by one unit of the input digital signal, passes through a D/A converter, and outputs it as an analog voltage;
The differential signal obtained by subtracting the unit-delayed signal is input, and the output is integrated into a D/A converter and an integrator with a chopper discharge circuit that integrates the output for one sampling period and discharges it at the beginning of the period. A D/A conversion circuit comprising: a second branch that outputs a voltage; and an adder that combines the outputs of the first branch and the second branch and outputs the result as an analog conversion output.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7426688U JPH01177619U (en) | 1988-06-06 | 1988-06-06 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7426688U JPH01177619U (en) | 1988-06-06 | 1988-06-06 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01177619U true JPH01177619U (en) | 1989-12-19 |
Family
ID=31299382
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7426688U Pending JPH01177619U (en) | 1988-06-06 | 1988-06-06 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01177619U (en) |
-
1988
- 1988-06-06 JP JP7426688U patent/JPH01177619U/ja active Pending