JPH021932U - - Google Patents
Info
- Publication number
- JPH021932U JPH021932U JP7999288U JP7999288U JPH021932U JP H021932 U JPH021932 U JP H021932U JP 7999288 U JP7999288 U JP 7999288U JP 7999288 U JP7999288 U JP 7999288U JP H021932 U JPH021932 U JP H021932U
- Authority
- JP
- Japan
- Prior art keywords
- converter
- gain amplifier
- converted
- programmable gain
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Analogue/Digital Conversion (AREA)
Description
第１図は本考案に係るＡＤ変換器の一実施例を
示す構成回路図、第２図は第１図におけるＰＧＡ
の具体的な構成を示す構成回路図、第３図は第１
図装置の１変形例を示す要部構成回路図、第４図
は従来のＡＤ変換器の構成を示す構成ブロツク図
、第５図は第４図装置の動作を示すタイムチヤー
トである。
２，３……プログラマブルゲインアンプ、４…
…ＡＤ変換部、５，６……ＤＡ変換部、９，９ａ
……オフセツト調整手段、１０，１０ａ……ゲイ
ン調整手段、１１……回路手段。
FIG. 1 is a configuration circuit diagram showing one embodiment of an AD converter according to the present invention, and FIG. 2 is a PGA in FIG. 1.
3 is a configuration circuit diagram showing the specific configuration of
4 is a block diagram showing the configuration of a conventional AD converter, and FIG. 5 is a time chart showing the operation of the device shown in FIG. 4. 2, 3...Programmable gain amplifier, 4...
...AD conversion section, 5, 6...DA conversion section, 9, 9a
...Offset adjustment means, 10, 10a...Gain adjustment means, 11...Circuit means.
Claims (1)
ンアンプに入力し、このプログラマブルゲインア
ンプの出力をＡＤ変換部でデジタル信号に変換し
て、前記変換すべきアナログ信号と前記デジタル
信号をＤＡ変換部で再びアナログ信号に変換した
信号との残差を再び前記プログラマブルゲインア
ンプに入力するとともにこのプログラマブルゲイ
ンアンプの利得を所定の値だけ大きくしてその出
力を前記ＡＤ変換部でデジタル信号に変換する操
作を繰返して行うＡＤ変換器において、 ＡＤ変換部の基準電圧入力を用いてゲインの調
整を行うゲイン調整手段と、プログラマブルゲイ
ンアンプの入力側でオフセツト電圧を調整するオ
フセツト調整手段と、ＤＡ変換部の出力をプログ
ラマブルゲインアンプの入力回路から切離すこと
のできる回路手段とを備えたことを特徴とするＡ
Ｄ変換器。[Claims for Utility Model Registration] An analog signal to be converted is input to a programmable gain amplifier, the output of the programmable gain amplifier is converted to a digital signal by an AD converter, and the analog signal to be converted and the digital signal are combined. The residual difference from the signal converted into an analog signal by the DA converter is input again to the programmable gain amplifier, and the gain of this programmable gain amplifier is increased by a predetermined value, and the output is converted to a digital signal by the AD converter. In an AD converter that repeatedly performs a conversion operation, a gain adjustment means that adjusts the gain using the reference voltage input of the AD conversion section, an offset adjustment means that adjusts the offset voltage on the input side of the programmable gain amplifier, and a DA and circuit means capable of separating the output of the conversion section from the input circuit of the programmable gain amplifier.
D converter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7999288U JPH021932U (en) | 1988-06-16 | 1988-06-16 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7999288U JPH021932U (en) | 1988-06-16 | 1988-06-16 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH021932U true JPH021932U (en) | 1990-01-09 |
Family
ID=31304839
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7999288U Pending JPH021932U (en) | 1988-06-16 | 1988-06-16 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH021932U (en) |
-
1988
- 1988-06-16 JP JP7999288U patent/JPH021932U/ja active Pending