JPH0250900U - - Google Patents
Info
- Publication number
- JPH0250900U JPH0250900U JP12678188U JP12678188U JPH0250900U JP H0250900 U JPH0250900 U JP H0250900U JP 12678188 U JP12678188 U JP 12678188U JP 12678188 U JP12678188 U JP 12678188U JP H0250900 U JPH0250900 U JP H0250900U
- Authority
- JP
- Japan
- Prior art keywords
- sample
- circuit
- output
- hold
- hold circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 2
- 238000005070 sampling Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
Description
第１図はこの考案の一実施例によるグリツジ除
去回路を示す回路図、第２図はこの考案のグリツ
ジ除去回路の動作を示す波形図、第３図は従来の
グリツジ除去回路を示す回路図、第４図はＤ／Ａ
変換器におけるグリツヂ発生の説明図、第５図は
従来のグリツジ除去回路の動作を示す波形図であ
る。
図において、１はバツフアアンプ、２はスイツ
チ回路、３はスイツチ駆動回路、４はホールドコ
ンデンサ、５はバツフアアンプ、６は切換スイツ
チ回路、７はスイツチ駆動回路、８はバツフアア
ンプ回路、１０はサンプルホールド回路を示す。
なお、図中、同一符号は同一、又は相当部分を示
す。
FIG. 1 is a circuit diagram showing a glitch removal circuit according to an embodiment of this invention, FIG. 2 is a waveform diagram showing the operation of the glitch removal circuit of this invention, and FIG. 3 is a circuit diagram showing a conventional glitch removal circuit. Figure 4 is D/A
FIG. 5, which is an explanatory diagram of the occurrence of glitches in a converter, is a waveform diagram showing the operation of a conventional glitch removal circuit. In the figure, 1 is a buffer amplifier, 2 is a switch circuit, 3 is a switch drive circuit, 4 is a hold capacitor, 5 is a buffer amplifier, 6 is a changeover switch circuit, 7 is a switch drive circuit, 8 is a buffer amplifier circuit, and 10 is a sample and hold circuit. show.
In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
ジタルデータに同期して、データの切替時に不必
要な信号成分を含む信号を入力とし、そのグリツ
ヂを除去する回路のスイツチ回路とホールドコン
デンサとバツフアアンプを備えたサンプルホール
ド回路を用いて、上記グリツヂ部分でないデジタ
ルデータに対して正しいアナログ出力をサンプル
する様にした回路において、上記サンプルホール
ド回路入力にバツフアアンプを備え、上記サンプ
ルホールド回路がホールド期間のとき前記サンプ
ルホールド回路出力を出力とし、上記サンプルホ
ールド回路がサンプル期間のとき、上記サンプル
ホールド回路入力前段より出力をする様にしたこ
とを特徴とするグリツヂ除去回路。 A sample equipped with a switch circuit, a hold capacitor, and a buffer amplifier, which is a circuit that synchronizes with digital data, such as the output of a digital-to-analog converter, and removes glitches by inputting a signal that includes unnecessary signal components when switching data. In a circuit that uses a hold circuit to sample a correct analog output for digital data that is not a grid part, a buffer amplifier is provided at the input of the sample and hold circuit, and when the sample and hold circuit is in a hold period, the sample and hold circuit samples a correct analog output. A glitch removal circuit characterized in that the output is an output, and when the sample and hold circuit is in a sampling period, the output is made from a stage preceding the input of the sample and hold circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12678188U JPH0250900U (en) | 1988-09-28 | 1988-09-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12678188U JPH0250900U (en) | 1988-09-28 | 1988-09-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0250900U true JPH0250900U (en) | 1990-04-10 |
Family
ID=31378609
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12678188U Pending JPH0250900U (en) | 1988-09-28 | 1988-09-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0250900U (en) |
-
1988
- 1988-09-28 JP JP12678188U patent/JPH0250900U/ja active Pending
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