JPS59134941U - analog to digital converter - Google Patents

analog to digital converter

Info

Publication number
JPS59134941U
JPS59134941U JP2784283U JP2784283U JPS59134941U JP S59134941 U JPS59134941 U JP S59134941U JP 2784283 U JP2784283 U JP 2784283U JP 2784283 U JP2784283 U JP 2784283U JP S59134941 U JPS59134941 U JP S59134941U
Authority
JP
Japan
Prior art keywords
voltage
value
analog
difference
digital converter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2784283U
Other languages
Japanese (ja)
Inventor
誠一郎 森
石橋 有
本田 敏和
実 中島
Original Assignee
日本電子株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電子株式会社 filed Critical 日本電子株式会社
Priority to JP2784283U priority Critical patent/JPS59134941U/en
Publication of JPS59134941U publication Critical patent/JPS59134941U/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

図は本考案に係るAD変換器の一実施例を示す要部構成
図である。     。 1・・・・・・減算回路、2・・・・・・増幅器、3・
・・・・・AD変換回路、4・・・・・・ディジタル加
算器、5・・・・・・上位コード発生回路、6・・・・
・・減算電圧発生回路、7・・・・・・基準電源、8・
・・・・・カウンタ、9・・・・・・比較器、10・・
・・・・アンド回路、11・・・・・・クロック回路。
The figure is a main part configuration diagram showing an embodiment of an AD converter according to the present invention. . 1...Subtraction circuit, 2...Amplifier, 3.
...AD conversion circuit, 4...Digital adder, 5...Upper code generation circuit, 6...
...Subtraction voltage generation circuit, 7...Reference power supply, 8.
...Counter, 9...Comparator, 10...
...AND circuit, 11...Clock circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 基準電圧を単位電圧としてステップ状に増加する減算電
圧六入カアナログ電圧との差をきり、該差電圧が前記単
位電圧よりも小さくなったとき、前記差電圧を適宜増幅
また後ディジタル変換して下位電圧値を得ると共に、前
記減算電圧に対応したディジタル値を求めて上位電圧値
を得、該上位電圧値と前記下位電圧値を合成して、前記
入力アナログ電圧のディジタル変換値を得るようにした
ことを特徴とするアナログ・ディジタル変換器。
The reference voltage is used as a unit voltage, and the difference between the six-input analog voltage and the subtracted voltage that increases stepwise is cut off, and when the difference voltage becomes smaller than the unit voltage, the difference voltage is appropriately amplified and then converted into a digital signal. While obtaining the voltage value, a digital value corresponding to the subtracted voltage is obtained to obtain an upper voltage value, and the upper voltage value and the lower voltage value are combined to obtain a digital conversion value of the input analog voltage. An analog-to-digital converter characterized by:
JP2784283U 1983-02-25 1983-02-25 analog to digital converter Pending JPS59134941U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2784283U JPS59134941U (en) 1983-02-25 1983-02-25 analog to digital converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2784283U JPS59134941U (en) 1983-02-25 1983-02-25 analog to digital converter

Publications (1)

Publication Number Publication Date
JPS59134941U true JPS59134941U (en) 1984-09-08

Family

ID=30158723

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2784283U Pending JPS59134941U (en) 1983-02-25 1983-02-25 analog to digital converter

Country Status (1)

Country Link
JP (1) JPS59134941U (en)

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