JPS59121940U - Digital/analog converter - Google Patents
Digital/analog converterInfo
- Publication number
- JPS59121940U JPS59121940U JP1376883U JP1376883U JPS59121940U JP S59121940 U JPS59121940 U JP S59121940U JP 1376883 U JP1376883 U JP 1376883U JP 1376883 U JP1376883 U JP 1376883U JP S59121940 U JPS59121940 U JP S59121940U
- Authority
- JP
- Japan
- Prior art keywords
- output
- digital data
- input digital
- digital
- analog conversion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Analogue/Digital Conversion (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案の第１の実施例の構成を示すブロック図
。第２図は本考案の第１の実施例における作用の説明に
供する波形図。第３図は本考案の第２の実施例の構成を
示すブロック図。第４図は本考案の第２の実施例におけ
る作用の説明に供する波形図。第５図は本考案の第３の
実施例の構成を示すブロック図。第６図は本考案の第３
の実施例における作用の説明に供する波形図。第７図は
本考案の第４の実施例の構成を示すブロック図。
第８図は本考案の第４の実施例における作用の説明に供
する波形図。
１およびＩＡ・・・遅延回路、２および３・・・ＤＡＣ
。
４、 ４Ａ、 ４Ｂ、 ５． ５Ａ、 ５ａ、
１２． １２Ａ。
１２Ｂ、１３．１３Ａおよび１３．・・・サンプルホー
ルド回路、６．６Ａおよび６Ｂ・・・タイミングコント
ロール回路、７．７Ａおよび７Ｂ・・・減算回路、８゜
８Ａおよび８Ｂ・・・リセット積分回路、９．９Ａおよ
び９Ｂ・・・非反転加算回路。FIG. 1 is a block diagram showing the configuration of a first embodiment of the present invention. FIG. 2 is a waveform diagram for explaining the operation in the first embodiment of the present invention. FIG. 3 is a block diagram showing the configuration of a second embodiment of the present invention. FIG. 4 is a waveform diagram for explaining the operation in the second embodiment of the present invention. FIG. 5 is a block diagram showing the configuration of a third embodiment of the present invention. Figure 6 is the third part of this invention.
FIG. 3 is a waveform diagram for explaining the operation in the embodiment. FIG. 7 is a block diagram showing the configuration of a fourth embodiment of the present invention. FIG. 8 is a waveform diagram for explaining the operation in the fourth embodiment of the present invention. 1 and IA...delay circuit, 2 and 3...DAC
. 4, 4A, 4B, 5. 5A, 5a,
12. 12A. 12B, 13.13A and 13. ...Sample hold circuit, 6.6A and 6B...Timing control circuit, 7.7A and 7B...Subtraction circuit, 8°8A and 8B...Reset integration circuit, 9.9A and 9B... Non-inverting adder circuit.
Claims (1)
タのアナログ変換値をサンプルホールドした第１の出力
に変換し、かつ前記入力デジタルデータの１ワ一ド期間
または２ワ一ド期間遅れた前記入力デジタルデータのア
ナログ変換値をサンプルホールドした第２の出力に変換
する変換手段゛ −と、前記第１の出力から前記第２の
出力を減算する減算手段と、該減算手段の出力を前記サ
ンプルホールドのサンプリング周期毎にリセットして積
分する積分手段と、前記第２出力と前記積分手段の出力
とを加算する加算手段とを備えてなることを特徴とする
デジタル／アナログ変換装置。The input digital data is supplied with input digital data, converts an analog conversion value of the input digital data into a sample-and-held first output, and is delayed by one word period or two word periods of the input digital data. a conversion means for converting an analog conversion value of 1 to a sample-held second output; a subtraction means for subtracting the second output from the first output; and a subtraction means for subtracting the second output from the first output; A digital/analog conversion device comprising: an integrating means that resets and integrates every cycle; and an adding means that adds the second output and the output of the integrating means.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1376883U JPS59121940U (en) | 1983-02-03 | 1983-02-03 | Digital/analog converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1376883U JPS59121940U (en) | 1983-02-03 | 1983-02-03 | Digital/analog converter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59121940U true JPS59121940U (en) | 1984-08-16 |
Family
ID=30145151
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1376883U Pending JPS59121940U (en) | 1983-02-03 | 1983-02-03 | Digital/analog converter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59121940U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5350722A (en) * | 1976-10-18 | 1978-05-09 | Kawai Musical Instr Mfg Co | Noise reducing circuit for digital tone color generator |
-
1983
- 1983-02-03 JP JP1376883U patent/JPS59121940U/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5350722A (en) * | 1976-10-18 | 1978-05-09 | Kawai Musical Instr Mfg Co | Noise reducing circuit for digital tone color generator |
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