JPS6045536U - DA converter - Google Patents
DA converterInfo
- Publication number
- JPS6045536U JPS6045536U JP13781783U JP13781783U JPS6045536U JP S6045536 U JPS6045536 U JP S6045536U JP 13781783 U JP13781783 U JP 13781783U JP 13781783 U JP13781783 U JP 13781783U JP S6045536 U JPS6045536 U JP S6045536U
- Authority
- JP
- Japan
- Prior art keywords
- differential input
- time
- converter
- input integrator
- side integration
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Analogue/Digital Conversion (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図及び第２図は従来のＤＡコンバーターを示し、第
１図はブロック図、第２図は各ブロックにおける波形と
タイミングを示すグラフ、第３図乃至第６図は本考案に
係るＤＡコンバーターの実施例を示し、第３図はブロッ
ク図、第４図は各ブロックにおける波形とそのタイミン
グを示すグラフ、第５図はタイミング回路の実施例を示
すブロックダイヤグラム、第６図は差動入力積分器の実
施例を示す回路図である。
１・・・定電流源、２・・・差動入力積分器、３・・・
第１のスイッチ部、４・・・第２のスイッチ部、５・・
・タイミング回路、６・・・サンプル・アンド・ホール
ド回 −路。Figures 1 and 2 show a conventional DA converter, Figure 1 is a block diagram, Figure 2 is a graph showing waveforms and timing in each block, and Figures 3 to 6 are DA converters according to the present invention. 3 is a block diagram, FIG. 4 is a graph showing waveforms in each block and their timing, FIG. 5 is a block diagram showing an example of a timing circuit, and FIG. 6 is a differential input integration diagram. FIG. 2 is a circuit diagram showing an embodiment of the device. 1... Constant current source, 2... Differential input integrator, 3...
First switch section, 4... Second switch section, 5...
- Timing circuit, 6... Sample and hold circuit - circuit.
Claims (1)
差動入力積分器と、該定電流源と上記差動入力積分器の
＋側及び−個入力端との間に夫々介挿された第１及び第
２のスイッチ部と、上記差動入力積分器からの出力信号
を入力とするサンプル・アンド・ホールド回路と、上記
差動入力積分器、第１、第２のスイッチ部及びサンプル
・アンド・ホールド回路に夫々作動信号を与えるための
タイミング回路とを備え、該タイミング回路は、単位デ
ータを変換する期間における上記第１のスイッチ部と上
記第２のスイッチ部の夫々のオン時間の合計時間が一定
時間となるように設定されていることを特徴とするＤＡ
コンバーター。 ２ 上記タイミング回路は、 単位データを変換する期間における差動入力積分器の＋
側積分時間と一側積分時間との合計時間が一定であるよ
うに設定されており、＋側の積分時期と一側の積分時期
に時間差を与えるようになっていることを特徴とする実
用新案登録請求の範囲第１項記載のＤＡコンバーター。[Claims for Utility Model Registration] 1. An integral type DA converter, which includes a constant current source,
a differential input integrator, first and second switch parts inserted between the constant current source and the + and - input terminals of the differential input integrator, and the differential input integrator; a sample-and-hold circuit that receives an output signal from the device; and a timing circuit that provides operating signals to the differential input integrator, the first and second switch sections, and the sample-and-hold circuit, respectively. The timing circuit is characterized in that the total time of the on-times of each of the first switch section and the second switch section during a period of converting unit data is set to be a constant time. DA to be
converter. 2 The above timing circuit is configured to control the + of the differential input integrator during the period of converting unit data.
A utility model characterized in that the total time of the side integration time and the one side integration time is set to be constant, and a time difference is given between the + side integration time and the one side integration time. A DA converter according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13781783U JPS6045536U (en) | 1983-09-07 | 1983-09-07 | DA converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13781783U JPS6045536U (en) | 1983-09-07 | 1983-09-07 | DA converter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6045536U true JPS6045536U (en) | 1985-03-30 |
| JPH0424659Y2 JPH0424659Y2 (en) | 1992-06-11 |
Family
ID=30309428
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13781783U Granted JPS6045536U (en) | 1983-09-07 | 1983-09-07 | DA converter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6045536U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5583336A (en) * | 1978-12-20 | 1980-06-23 | Advantest Corp | Digital-to-analog converter |
| JPS57203328A (en) * | 1981-06-10 | 1982-12-13 | Matsushita Electric Ind Co Ltd | Digital-to-analog converter |
-
1983
- 1983-09-07 JP JP13781783U patent/JPS6045536U/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5583336A (en) * | 1978-12-20 | 1980-06-23 | Advantest Corp | Digital-to-analog converter |
| JPS57203328A (en) * | 1981-06-10 | 1982-12-13 | Matsushita Electric Ind Co Ltd | Digital-to-analog converter |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0424659Y2 (en) | 1992-06-11 |
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