JPS61139025U - - Google Patents
Info
- Publication number
- JPS61139025U JPS61139025U JP1985022468U JP2246885U JPS61139025U JP S61139025 U JPS61139025 U JP S61139025U JP 1985022468 U JP1985022468 U JP 1985022468U JP 2246885 U JP2246885 U JP 2246885U JP S61139025 U JPS61139025 U JP S61139025U
- Authority
- JP
- Japan
- Prior art keywords
- output voltage
- variable
- level
- generation means
- cmos element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims description 2
- 230000008054 signal transmission Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Pulse Circuits (AREA)
- Networks Using Active Elements (AREA)
Description
第１図は本考案にかかる信号遅延回路の一実施
例の構成図、第２図は第１図のＣＭＯＳ素子の特
性を表したグラフ、第３図は第１図のレベル変換
手段の他の構成例を示した図、第４図及び第５図
は信号遅延回路の従来例の構成図である。
１０…可変電圧発生手段、２０，２０１，２０
２…ＣＭＯＳ素子、３０…レベル変換手段。
FIG. 1 is a block diagram of an embodiment of the signal delay circuit according to the present invention, FIG. 2 is a graph showing the characteristics of the CMOS device shown in FIG. 1, and FIG. FIGS. 4 and 5 are diagrams illustrating configuration examples of conventional signal delay circuits. 10...Variable voltage generating means, 20, 20 1 , 20
2 ...CMOS element, 30...Level conversion means.
Claims (1)
出力電圧の大きさに応じて信号の伝達時間が連続
的に変わるＣＭＯＳ素子と、 入力信号のレベルを前記ＣＭＯＳ素子の入力ス
レツシヨールドレベルに比例して変換するレベル
変換手段、 とを具備したことを特徴とする信号遅延回路。[Claims for Utility Model Registration] Variable voltage generation means whose output voltage is variable; and a signal transmission time that operates with the output voltage of the variable voltage generation means and changes continuously according to the magnitude of this output voltage. A signal delay circuit comprising: a CMOS element; and level conversion means for converting the level of an input signal in proportion to an input threshold level of the CMOS element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985022468U JPS61139025U (en) | 1985-02-19 | 1985-02-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985022468U JPS61139025U (en) | 1985-02-19 | 1985-02-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61139025U true JPS61139025U (en) | 1986-08-28 |
Family
ID=30514788
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1985022468U Pending JPS61139025U (en) | 1985-02-19 | 1985-02-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61139025U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1997024806A1 (en) * | 1995-12-28 | 1997-07-10 | Advantest Corporation | Semiconductor integrated circuit device with delay error correcting circuit |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6041320A (en) * | 1983-08-17 | 1985-03-05 | Fujitsu Ltd | Delay circuit |
-
1985
- 1985-02-19 JP JP1985022468U patent/JPS61139025U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6041320A (en) * | 1983-08-17 | 1985-03-05 | Fujitsu Ltd | Delay circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1997024806A1 (en) * | 1995-12-28 | 1997-07-10 | Advantest Corporation | Semiconductor integrated circuit device with delay error correcting circuit |