JPS63163536U - - Google Patents

Info

Publication number
JPS63163536U
JPS63163536U JP5403387U JP5403387U JPS63163536U JP S63163536 U JPS63163536 U JP S63163536U JP 5403387 U JP5403387 U JP 5403387U JP 5403387 U JP5403387 U JP 5403387U JP S63163536 U JPS63163536 U JP S63163536U
Authority
JP
Japan
Prior art keywords
digit
adder
input
group
numerical values
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5403387U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP5403387U priority Critical patent/JPS63163536U/ja
Publication of JPS63163536U publication Critical patent/JPS63163536U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図および第2図は本考案に係る多入力加算
器の一実施例の構成を示すブロツク図、第3図は
パイプライン処理を行う場合の構成を示すブロツ
ク図、第4図、第5図は従来の多入力加算器の構
成を示すブロツク図である。 11〜14,16〜22……加算器、15,2
3……パラレル加算器、24〜26……レジスタ
1 and 2 are block diagrams showing the configuration of an embodiment of a multi-input adder according to the present invention, FIG. 3 is a block diagram showing the configuration when pipeline processing is performed, and FIGS. 4 and 5 The figure is a block diagram showing the configuration of a conventional multi-input adder. 11-14, 16-22... Adder, 15, 2
3...Parallel adder, 24-26...Register.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 複数の入力データが入力され、これらの入力デ
ータの同一桁の数値を加算して2桁の数値の集合
として出力する第1の加算器群と、2つの多桁デ
ータが入力されこれらのデータを加算する第2の
加算器とを有し、前記第1の加算器群の出力の各
桁の数値を前記第2の加算器の各々の入力の対応
する桁に入力するようにした多入力加算器。
A first group of adders receives a plurality of input data, adds the same-digit numerical values of these input data, and outputs the result as a set of two-digit numerical values; a second adder that performs addition, and the numerical value of each digit of the output of the first adder group is input to a corresponding digit of each input of the second adder. vessel.
JP5403387U 1987-04-09 1987-04-09 Pending JPS63163536U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5403387U JPS63163536U (en) 1987-04-09 1987-04-09

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5403387U JPS63163536U (en) 1987-04-09 1987-04-09

Publications (1)

Publication Number Publication Date
JPS63163536U true JPS63163536U (en) 1988-10-25

Family

ID=30880647

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5403387U Pending JPS63163536U (en) 1987-04-09 1987-04-09

Country Status (1)

Country Link
JP (1) JPS63163536U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5275141A (en) * 1975-12-18 1977-06-23 Fujitsu Ltd Accumulator

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5275141A (en) * 1975-12-18 1977-06-23 Fujitsu Ltd Accumulator

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