JPH0289540U - - Google Patents
Info
- Publication number
- JPH0289540U JPH0289540U JP16655488U JP16655488U JPH0289540U JP H0289540 U JPH0289540 U JP H0289540U JP 16655488 U JP16655488 U JP 16655488U JP 16655488 U JP16655488 U JP 16655488U JP H0289540 U JPH0289540 U JP H0289540U
- Authority
- JP
- Japan
- Prior art keywords
- arithmetic
- arithmetic unit
- registers
- pipeline
- holding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 4
Description
第１図はこの考案の一実施例による浮動小数点
演算器のブロツク図、第２図はこの考案の一実施
例の実施例のタイミング図、第３図は従来の浮動
小数点演算器のブロツク図、第４図は従来の浮動
小数点演算器の実行例のタイミング図である。
図において３１，３２，３３，３４は入力レジ
スタ、８２は演算結果保持レジスタ、５２，６２
はパイプラインレジスタである。なお、図中、同
一符号は同一または相当部分を示す。
FIG. 1 is a block diagram of a floating point arithmetic unit according to an embodiment of this invention, FIG. 2 is a timing diagram of an embodiment of this invention, and FIG. 3 is a block diagram of a conventional floating point arithmetic unit. FIG. 4 is a timing diagram of an example of execution of a conventional floating point arithmetic unit. In the figure, 31, 32, 33, 34 are input registers, 82 is a calculation result holding register, 52, 62
is a pipeline register. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.
Claims (1)
個以上持ち、演算結果を演算器内部に保持するた
めの演算結果保持レジスタを複数持ち、パイプラ
イン加算器とパイプライン乗算器が同時に動作す
ることを特徴とする浮動小数点演算器。 4 input registers to hold input data
A floating-point arithmetic unit having a plurality of arithmetic result holding registers for holding arithmetic results inside the arithmetic unit, and having a pipeline adder and a pipeline multiplier operating simultaneously.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16655488U JPH0289540U (en) | 1988-12-23 | 1988-12-23 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16655488U JPH0289540U (en) | 1988-12-23 | 1988-12-23 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0289540U true JPH0289540U (en) | 1990-07-16 |
Family
ID=31454039
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16655488U Pending JPH0289540U (en) | 1988-12-23 | 1988-12-23 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0289540U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007295128A (en) * | 2006-04-21 | 2007-11-08 | Daihen Corp | Logic integrated circuit and source of circuit for operation thereof, and computer readable recording medium for recording the same |
-
1988
- 1988-12-23 JP JP16655488U patent/JPH0289540U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007295128A (en) * | 2006-04-21 | 2007-11-08 | Daihen Corp | Logic integrated circuit and source of circuit for operation thereof, and computer readable recording medium for recording the same |
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