JPH0223751U - - Google Patents
Info
- Publication number
- JPH0223751U JPH0223751U JP10258088U JP10258088U JPH0223751U JP H0223751 U JPH0223751 U JP H0223751U JP 10258088 U JP10258088 U JP 10258088U JP 10258088 U JP10258088 U JP 10258088U JP H0223751 U JPH0223751 U JP H0223751U
- Authority
- JP
- Japan
- Prior art keywords
- address
- holding
- holding means
- information
- calculation means
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Image Input (AREA)
Description
第１図は本考案に係るアドレス生成装置を適用
した画像処理装置の構成図、第２図は第１図に示
したアドレス生成装置の具体的な構成例を示す図
、第３図は画像メモリの物理的な１次元配列を示
す図、第４図は画像メモリの論理的な２次元配列
を示す図、第５図は第４図のような２次元配列に
対応したアドレスを生成する従来のアドレス生成
装置の概略構成図である。
１…プロセツサ、２…メモリ、３…画像メモリ
、４…アドレス生成装置、１０…命令レジスタ、
１１…情報保持手段、１２…中間保持手段、１３
…演算手段、１４…出力手段、Ｒ０，Ｒ１…レジ
スタ。
FIG. 1 is a block diagram of an image processing device to which the address generation device according to the present invention is applied, FIG. 2 is a diagram showing a specific configuration example of the address generation device shown in FIG. 1, and FIG. 3 is an image memory 4 is a diagram showing a logical 2-dimensional array of image memory, and FIG. FIG. 1 is a schematic configuration diagram of an address generation device. DESCRIPTION OF SYMBOLS 1...Processor, 2...Memory, 3...Image memory, 4...Address generation device, 10...Instruction register,
11... Information holding means, 12... Intermediate holding means, 13
...Arithmetic means, 14...Output means, R0 , R1 ...Registers.
Claims (1)
保持する情報保持手段と、１つ前の時点に生成さ
れたアドレスを保持する中間保持手段と、前記情
報保持手段からの所定情報と中間保持手段からの
アドレスとを演算させアドレスを生成する演算手
段と、演算手段で生成されたアドレスを出力する
出力手段とを備えていることを特徴とするアドレ
ス生成装置。 Information holding means for holding predetermined information in a two-dimensional array so that the settings can be changed arbitrarily, intermediate holding means for holding an address generated at the previous point in time, and predetermined information from the information holding means and intermediate holding means. 1. An address generation device comprising: a calculation means for generating an address by calculating an address from the calculation means; and an output means for outputting the address generated by the calculation means.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10258088U JPH0223751U (en) | 1988-08-02 | 1988-08-02 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10258088U JPH0223751U (en) | 1988-08-02 | 1988-08-02 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0223751U true JPH0223751U (en) | 1990-02-16 |
Family
ID=31332615
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10258088U Pending JPH0223751U (en) | 1988-08-02 | 1988-08-02 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0223751U (en) |
-
1988
- 1988-08-02 JP JP10258088U patent/JPH0223751U/ja active Pending