JPH03220668A - Product sum arithmetic unit - Google Patents

Abstract

PURPOSE:To execute product sum arithmetic by obtaining carry save adder (CSA) constitution by a full adder for an accumulator without using a carry propagation adder (CPA). CONSTITUTION:On the output stage of a CSA 2, the data output is expressed by the two bits of Sum and Carry concerning a bit equipped with the same weight. Even at an accumulator 3 with the CSA constitution, the constitution is caused by the CSA itself and therefore, the output is similarly expressed by the two bits of the Sum and the Carry as well. Therefore, the accumulator 3 with the CSA constitution obtains the input/output relation of 4 inputs / 2 outputs and is composed of FA in two steps. By adding these two bits at a CPA 6 after ending accumulation, the bit can be converted to a normal binary number. Thus, an arithmetic procedure at the CPA 6 is not interposed to an accumulation cycle, the product sum arithmetic can be accelerated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a product-sum calculator, and more particularly to a product-sum calculator that performs arithmetic operations.

[Conventional technology]

Conventionally, this type of product-sum calculation unit is generally configured by combining a parallel multiplier and an accumulator using a carry propagation adder (CPA). Third
What is shown in the figure is a block diagram of a conventional 4-bit product-sum calculator, which includes a manual data latch 13 that includes four registers (Reg) corresponding to (XO to X3) as multiplicands, and a multistage full adder (FA). ), a parallel multiplier including a carry save adder (C3A) 14 configured by arranging a carry save adder (C3A), an accumulator 15 having a carry save adder (C3A) configuration, and a carry propagation adder (CPA).
16 and an accumulation register 17.

In FIG. 3, the output of the input data latch 13 is input to a carry save adder (C3A) 14, where the partial products are added together, and for bits with the same weight, Phase signal (hereinafter,
The signal is converged to two pins I~, a carry signal (hereinafter abbreviated as Carry) and a carry signal (hereinafter abbreviated as Carry). Note that in FIG. 3, the mark * represents "O input" (this also applies to FIGS. 1-2).

The multiplication result is obtained by adding the above convergence results in the carry propagation adder (CPA) 16, but a full adder (FA) is connected to the input side of the carry propagation adder (CPA) 16 at the final stage.
By providing the accumulator 15 which is arranged in the following manner, the carry propagation adapter (CPA)
The sum-of-products operation is executed by inputting the inputs to the multiplication register 16 by three people and making it possible to add the multiplication result to the accumulation register 17 or perform -g calculation.

[Problem to be solved by the invention]

In the conventional product-sum calculator described above, the carry propagation adder (CPA) operation is included in the acquisition cycle during calculation. For this reason,
There is a drawback that it is difficult to shorten the cycle time when performing product-sum operations continuously.

[Means to solve the problem]

The product-sum calculator of the present invention has at least four inputs, two of which are a sum signal obtained as the sum of partial products of multiplication and a digit signal, and the remaining two inputs are N (positive integer ) bits.

〔Example〕

Next, the present invention will be explained with reference to the drawings. The first embodiment of the present invention is a block diagram showing a 4-bit product-sum calculator. In FIG. 1, absolute value expression is used for simplicity, and the configuration is shown along the flow of data of only the multiplicand.

As shown in FIG. 1, in this embodiment, the multiplicand (XO~
An input data latch including four registers (Reg) corresponding to 1.X3). and a carry-save adder (C8A) 2 that is configured by arranging multi-stage full adders (FA).
An accumulator 3 having a carry-save adder (C3A) configuration, a parallel multiplier that combines the two, an accumulation register 4, and an accumulation carry signal latch 5.
, carry propagation adder (CPA) 6,
It is composed of:

In FIG. 1, the multiplicands of (XO to X3> are the input data latch 1 including the corresponding register (Reg).
and is input to the carry save adder (C3A) 2 formed by a full adder (FA) array configuration. In the carry save adder (C3A) 2, the latched multiplicand is taken in and the sum of the multiplication partial products is calculated, and the calculation result is sent to the carry propagation adder (C3A) configuration.
sent to. In the accumulator 3, the output of the carry save adder (C3A) 2 and the accumulation result latch output from the accumulation register 4 are added and subtracted, and the calculation output is input to the accumulation register 4. Ru.

At the output stage of the carry save adder (C3A), 2, its data output is represented by two bits, Sum and Carry, for bits with the same weight. Also,
Even in the accumulator 3 having a carry save adder (CSA) configuration, the structure is similar to that of a carry save adder (CSA).
8A) itself, its output is also S
It is represented by two bits: um, Carr, and y. Therefore, the Akinimulator 3 configured as a carry save adder (C3A) has an input/output relationship of 4 human power/2 outputs, and is composed of a 2-stage full adder (FA).

Furthermore, since the result of the akineem ratio is represented by two bits, Sum and Carry, for each bit having the same weight, after the accumulation is completed, in the carry propagation adder (CPA) 6,
By adding these 2 bits, it is possible to convert to a normal binary number. Therefore, the accumulation cycle includes a carry propagation adder (
Since the calculation procedure in CPA) 6 does not intervene, it is possible to speed up the product-sum calculation.

Next, a second embodiment of the present invention will be described. FIG. 2 is a block diagram showing a second embodiment. As shown in FIG. 2, this embodiment is configured by arranging an input data latch 7 including four registers (Reg) corresponding to multiplicands (XO to X3) and a multistage full adder (FA). a parallel multiplier including a carry save adder <C3A) 8, an accumulator 9 having a carry save adder (C3A) configuration, an accumulation register 0, an accumulation carry signal latch 11, and a carry propagation adder. (CPA) 12.

In FIG. 2, the difference between this embodiment and the first embodiment is that a full adder (FA
) and provide an overflow guard bit,
Furthermore, a corresponding register is added to the accumulation register 10 as well. Although it is difficult to detect overflow with an accumulator using a carry save adder (CS A, ), by providing the above overflow guard bit, the guard pitch I~ is 2 bits, so
There is an advantage that overflow in the accumulation is avoided up to three times.

〔Effect of the invention〕

As explained in detail below, the present invention provides an accumulator with a carry save adder (CS) using a full adder without using a carry propagation adder (CPA).
A) With the configuration, there is an effect that the sum of products operation can be executed at high speed.

[Brief explanation of drawings]

1 and 2 are block diagrams showing first and second embodiments of the present invention, respectively, and FIG. 3 is a block diagram showing a conventional example. In the figure, 1, 7.13--input data latch, 2, 8.14--carry save adder (C
3A), 3,9.15...accumulator,
410.17...Accumulation register, 5°11...Accumulation carry latch, 6°12, 16...Carry propagation adder (CPA).

Claims (1)

[Claims] Among at least four inputs, two inputs are the sum signal and carry signal obtained as the sum of partial products of multiplication, and the remaining two inputs are the accumulation results obtained as the output of a predetermined accumulator. and the carry signal, and the N (positive integer) bit accumulator is formed by a carry-save adder having two outputs corresponding to the four inputs. Sum operator.