JPH0566924A - Product sum computing element - Google Patents

Abstract

PURPOSE:To prevent the reduction of the computing speed of the data of a complement form of '2' for a product sum computing element which can deal with both types of data of the complement form of '2' and a no-code absolute value form. CONSTITUTION:The data of a no-code absolute value form are divided into a part concerning the highest order bit and a part concering only other bits in regard of the multiplication process by the instruction of a selection signal 35. The multiplication of the former part is carried out by a 16-bit adder 31, and the multiplication of the latter part is carried out by a (16X16)-bit multiplier 15 respectively. The computing result of the adder 31 is added to the higher order bit part of the computing result of the multiplier 15 by an adder 33 and inputted to a selector 34. The selector 34 outputs the received result of addition as it is by the instruction of the signal 35. This outputted result is inputted to an adder 17 together with the lower order bits of the computing result of the adder 15. Then the adder 17 and an accumulator 18 totalize successively these computing results. In regard of the data of a complement form of '2', the higher order bits of the computing result of the adder 15 are inputted to the adder 17 via the selector 34. Meanwhile the lower rank bits are directly inputted to the adder 17 respectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital circuit, and more particularly to a product-sum calculator used for calculating digital data.

[0002]

2. Description of the Related Art Normally, digital signals are often displayed in 2's complement which is signed data. For example, 16
The bit 2's complement display data is represented as shown in FIG. In this figure, the most significant bit b15 is a sign bit, and represents a positive or negative number corresponding to the value "0" or "1". Therefore, in 16 bits, the decimal number is "-3276".
Data of 8 "to" 32767 "can be handled.

On the other hand, in a digital signal processing circuit such as a digital filter, a product-sum calculator is generally used to perform various kinds of signal processing.

FIG. 5 shows a product-sum calculator used for 16-bit 2's complement display data. In this figure, [] indicates the bit width of data.

The product-sum calculator is provided with a 16-bit X register 13 and a 16-bit Y register 14 for holding the input 16-bit X input data 11 and Y input data 12, respectively. 16 from each of these registers
Bit data is output and input to a 16-bit × 16-bit multiplier 15. Multiplier 15
The 31-bit multiplication result data output from is temporarily held in the 31-bit product register 16 and input to one input terminal of the adder 17. The output of the adder 17 is input to the accumulator 18. This accumulator 18
The output 19 is divided into two, one of which is output as the product-sum output data, and the other is input to the other input terminal of the adder 17. It is assumed here that the accumulator 18 has a maximum accumulation result of 40 bits, and that the accumulator 18 also has 40 bits.

Further, the X register 13, the Y register 14,
A clock 20 is supplied to the product register 16 and the accumulator 18, and data acquisition and output are performed in synchronization with the timing.

However, in the product-sum calculator having such a configuration, since the multiplier 15 has 16 bits × 16 bits, as long as 16-bit multiplication is performed, only data in 2's complement display can be handled, and digital multiplication is possible. Unsigned absolute value format data, which is another data format used in processing, cannot be handled. This is because, in this unsigned absolute value format data, as shown in FIG.
The sign bit b16 is provided in addition to the 16 bits up to 15, and multiplication is performed with this bit set to "0".
This is because a multiplier of 17 bits × 17 bits is required. For this reason, conventionally, when it is necessary to handle data in the unsigned absolute value format as well as the 2's complement format, the product-sum calculator as shown in FIG. 6 has been used. In this figure, the same parts as those in FIG. The product-sum calculator is provided with a 17-bit × 17-bit multiplier 21, the input side of which is connected to the X register 13 and the Y register 14. Multiplier 21
The output side of is connected to a 40-bit adder 17 via a 33-bit product register 22. Other configurations are the same as those in FIG. [] Indicates the bit width of the data.

In this product-sum calculator, the multiplier 21 is 17
A bit × 17 bit operation is performed, and the output has a width of 33 bits. Therefore, the product register 22 needs to have 33 bits.

[0009]

As described above, in order to handle both 2's complement format data and unsigned absolute value format data in the conventional product-sum calculator, the sign of the unsigned absolute value format data is used. It was necessary to use a multiplier that is one bit larger for the bits. Therefore, for example, even when handling 16-bit 2's complement data, 17 bits × 17
Since multiplication of bits is performed, there is a problem that the calculation speed is reduced.

Therefore, there is a problem that the above problems must be solved.

The present invention has been made to solve the above problems, and can handle both 2's complement format data and unsigned absolute value format data, and also handles 2's complement format data. An object of the present invention is to obtain a product-sum calculator that does not reduce the calculation speed in some cases.

[0012]

A product-sum calculator according to the present invention is a product-sum calculator that can handle two types of data in 2's complement display format and data in unsigned absolute value format. )
First arithmetic means for multiplying the most significant bit of unsigned absolute value format data, and (ii) Multiplication only for bits other than the most significant bit of unsigned absolute value format data, and multiplication for 2's complement display format data And (iii) third computing means for obtaining a multiplication result of unsigned absolute value format data from the outputs of the first and second computing means,
(iv) It has a selection means for selecting either one of the multiplication result obtained for the 2's complement display format data by the second calculation means and the output of the third calculation means.

[0013]

In the multiply-accumulate operator according to the present invention, the multiplication of unsigned absolute value format data is divided into a portion related to the most significant bit and a portion related to only the other bits, thereby reducing the number of multiplication bits. Is possible.

[0014]

The present invention will be described in detail with reference to the following examples.

FIG. 1 shows a product-sum calculator in an embodiment of the present invention. In this figure, the same parts as those in the conventional example (FIGS. 5 and 6) are designated by the same reference numerals, and the description thereof will be omitted as appropriate. Further, also in this embodiment, a case of performing 16-bit × 16-bit multiplication will be described. In the data in the figure, [] indicates the bit width.

In this product-sum calculator, X register 13 and Y
The output of the register 14 is branched into two and connected to one input terminal of each of the 16-bit × 16-bit multiplier 15 and the 16-bit adder 31. The multiplier 15 is the same as that shown in the conventional example (FIG. 5). 31-bit data is output from the multiplier 15 and input to the product register 16. The 17-bit output from the adder 31 is input to one input terminal of the 17-bit adder 33 via the register 32. The other input terminal of the adder 33 has a sign extension of 2 in the upper 15 bits of the product register 16.
A total of 17 bits including bit 36 are input. The upper 15 bits of the product register 16 are also input to one input terminal of a selector 34 connected to the next stage of the adder 33. The 17-bit output from the adder 33 is input to the other input terminal of the selector 34. The selector 34 selects and outputs one of the upper 15 bits of the product register 16 and the output (17 bits) of the adder 33 according to the selection signal (Tc) 35. This selection signal 35 is output to the X register 1
3 and the Y register 14 are also input.

The output of the selector 34 is input to one input terminal of the adder 17 together with the lower 16 bits of the product register 16. The other input terminal of the adder 17 is connected to one of the branch outputs of the accumulator 18 connected to the next stage (4
0 bit) is input. Other configurations are the same as those in FIG. 5 or FIG.

The operation of the product-sum calculator having the above configuration will be described. First, a case of performing multiplication on unsigned absolute value format data will be described with reference to FIG.

In the X register 13 and the Y register 14,
16-bit data as shown in FIGS. 2A and 2B are input. In this figure, for example, X <15: 0>
Represents bits 0 to 15 of the data input to the X register 13. At this time, these registers are in the mode corresponding to the data in the unsigned absolute value format according to the instruction of the selection signal 35. For this reason,
The X register 13 sets the input data as data in which the most significant bit X <15> is set to “0” (FIG. 2C) and other than the most significant bit X <15> (in FIG. (D)) and input to the multiplier 15 and the adder 31 at the timing of the clock 20, respectively. Similarly, the Y register 14 converts the input data into the most significant bit Y <15.
> Is set to “0” (FIG. 2 (e)) and data other than the most significant bit Y <15> is set to “0” (FIG. 2 (f)). To enter. That is, as shown in (g) of the same figure, this multiplication is performed by expanding it into the form of the following expression (1).

Y <14: 0> · X <14: 0> + Y <15> · X <15: 0> + X <15> · Y <15: 0> (1) of the first term of this formula As described above, the operation is executed by the multiplier 15 as a multiplication of 16 bits together with "0" set in the most significant bit, and the product register is obtained as 31-bit data as shown in FIG. 2 (h). 16 is input.

On the other hand, the second term of the equation (1) is "0" when Y <15> is "0", and the upper bit is X <15: 0> when Y <15> is "1". The data has a digit structure as shown in FIG. The third term is X
When <15> is "0", it is "0", and X <15> is "1".
In the case of, the upper bits are data with Y <15: 0>, and the digit configuration is as shown in FIG. Therefore, the adder 31 eventually adds X <15: 0> and Y <15: 0>, and the addition result ((k) in the figure) is input to the register 32 as 17-bit data. It

Now, the upper 15 bits of the 31 bits stored in the product register 16, that is, the upper 15 bits of the first term of the equation (1), are read at the timing of the clock 20 and are read as shown in FIG. 2) 36 of sign extension is added as shown in), and 17-bit data is input to the adder 33. On the other hand, the adder 3 from the register 32
The addition result of 1, that is, the addition result of the second term and the third term of the equation (1) ((k) in the same figure) is read at the timing of the clock 20 and input to the adder 33. And adder 3
In 3, the addition is performed, and the addition result is selected by the selector 34.
To enter.

In this case, since the mode corresponding to the unsigned absolute value format data is instructed by the selection signal 35, the selector 34 outputs the addition result of the adder 33 as it is, and the lower 16 bits of the product register 16 are output. Adder 1 with bits
Type in 7. Then, in the same manner as in the conventional example (FIGS. 5 and 6), the accumulation is sequentially performed.

On the other hand, the multiplication on the data of the two's complement format is the same as in the case of the conventional example (FIG. 5). That is, the X register 13 and the Y register 14 have the selection signal 3
In accordance with the instruction of 5, the data of the two's complement format input to each is input to the multiplier 15 as it is, and the product register 16
Holds the multiplication result. However, in this case, the upper 15 bits of the product register 16 are directly input to the selector 34 and output as they are according to the instruction of the selection signal 35.
The output from the selector 34 is the lower 1 of the product register 16.
It is input to the adder 17 together with 6 bits. That is,
In the case of 2's complement format data, the contents of the product register 16 are directly input to the adder 17, and
Since the calculation is also a 16-bit × 16-bit multiplication,
The calculation process is exactly the same as in the conventional example (FIG. 5). Therefore, it is possible to secure the same calculation speed as the conventional one.

[0025]

As described above, according to the present invention,
Since the multiplication of the unsigned absolute value format data is divided into the portion related to the most significant bit and the portion related to only the other bits, the number of multiplication bits can be reduced. Therefore, there is an effect that it is possible to avoid a decrease in the multiplication speed of the data of the two's complement format, which is caused by handling the data of the unsigned absolute value format.

[Brief description of drawings]

FIG. 1 is a block diagram showing a product-sum calculator in an embodiment of the present invention.

FIG. 2 is an explanatory diagram for explaining an arithmetic operation of the product-sum calculator for unsigned absolute value format data.

FIG. 3 is an explanatory diagram showing a bit configuration of 2's complement data.

FIG. 4 is an explanatory diagram showing a bit configuration of data in an unsigned absolute value format.

FIG. 5 is a block diagram showing a conventional product-sum calculator that can handle only data in 2's complement format.

FIG. 6 is a block diagram showing a conventional product-sum calculator that can handle both 2's complement format data and unsigned absolute value format data.

[Explanation of symbols]

 13 X register 14 Y register 15 Multiplier (second operation means) 16 Product register 31 16-bit adder (first operation means) 32 Register 33 17-bit adder (third operation means) 34 Selector (Selection means) 35 selection signal

Claims (1)

[Claims] 1. A multiply-accumulate operator capable of handling two types of data in 2's complement display format and data in unsigned absolute value format, the first summing operation performing multiplication on the most significant bit of unsigned absolute value format data. Of the unsigned absolute value format data, second multiplication means for performing multiplication only on bits other than the most significant bit of the unsigned absolute value format data, and multiplication for the 2's complement display format data, and first and second computation means. Of the output of the third arithmetic means, the third arithmetic means for obtaining the multiplication result of the unsigned absolute value format data from the output, and the multiplication result obtained for the two's complement display format data by the second arithmetic means. And a selecting means for selecting either one of the above.