JPS59197936A - Digital signal processing system - Google Patents

Abstract

PURPOSE:To add a simple change to a fixed-point circuit and use directly its multiplied results as the solution of integer calculation by registering an integer multiplier and integer multiplicant in respective registers by shifting their digital positions in case of multiplication between integers. CONSTITUTION:In the case of multiplication between ordinary data, data of the multiplier and multiplicant are inputted into registers A and B through selectors E and F from a register for data memory, respectively, and the multiplication is performed at a multiplier C by a fixed-point system, and then, the solution is outputted to an accumulator D. Even in the case of multiplication between integers, data of the multiplier and multiplicant are added to the registers A and B through the selectors E and F and, at the same time, data from an address register H are added to the registers A and B through the selectors E and F in the same way. The multiplier and multiplicant are registered from the highest ranked one. The registers A and B are constituted so that the data can be registered under a condition where their digital positions are shifted. Moreover, by adding a registering instruction, multiplied results between integers are used as solutions of integer calculation.

Description

Detailed Description of the Invention (a) 9 Technical Field of the Invention The present invention relates to the configuration of a multiplication block for digital signal processing, and particularly when rounding the lower bits of a multiplier result, the position of the multiplier and multiplicand is This relates to a method that allows integer operations by setting.

(b), Prior Art and Problems FIG. 1 shows the configuration of a multiplier section of a DSP according to the prior art.

In the figure, A and B are registers, C is a multiplication circuit, and D is an accumulator.

The product of the values placed in registers A and B is the accumulator D.
is output to.

FIG. 2 is a diagram for explaining the operation of the circuit shown in FIG. 1.

In Figure 2, when using a fixed point system as a multiplier, for example, the data length is 8 bits and the decimal point position is MSB and 2.
When taken between bits, the bit configuration resulting from multiplication is as shown in FIG.

In an actual circuit, if the data handled by the DSP is 8 bits, the bits marked with an "X" in the solution are discarded by truncation or rounding, so the value of the upper 8 bits without the "X" mark is taken as the solution.

In general operations, the lower bits can be discarded (or rounded off) as shown above, but
When performing integer multiplication (that is, multiplying with the decimal point position of the multiplicand being below the LSB), it may be desired to output 8 bits including the 7 bits marked with an X in FIG. 2 as a solution.

For example, when numeric data is extracted one after another from a numerical table in the calculation of a Fourier series, a situation like this occurs when calculating the address of the numeric data.

In such a case, this problem can be solved by adding a circuit that selects the upper 8 bits or the lower 8 bits to the conventional fixed-point multiplication circuit, but the For DPS, which is the main purpose, there will be an increase in circuits for that purpose (accumulator and multiplication circuits will be increased)
There is a drawback.

(C)9 Purpose of the Invention The purpose of the present invention is to eliminate the above-mentioned drawbacks of the prior art;
It is an object of the present invention to provide a method in which a multiplication result becomes a solution to an integer operation by taking into consideration the digit positions of a multiplier and a multiplicand.

(d) 9 Structure of the Invention According to the present invention, a fixed-point multiplication circuit composed of a register for storing a multiplier, a register for storing a multiplicand, a multiplication circuit, and an accumulator can perform multiplication between integers. When implemented, the present invention is achieved by providing a digital signal processing method characterized in that when the integer multiplier and multiplicand are placed in the register, the digit positions can be shifted.

(e) 1 Embodiment of the Invention The present invention utilizes the fact that by shifting the digits when inputting a number, the digits of the solution can be shifted isometrically. This also enables fixed-point multiplication if necessary.

FIG. 3 is a diagram showing an embodiment of the present invention.

In FIG. 3, E and F are selectors, G is a data memory register, H is an address register, and other symbols are the same as in FIG. 1.

FIG. 4 is a diagram for explaining the operation of FIG. 3.

The present invention will be described in detail below with reference to FIG.

In the case of ordinary data multiplication, the multiplier and multiplicand data are transferred from data memory register G to selector E, respectively.
The signals are input to registers A, B via F, multiplied by a fixed-point method in multiplier C, and the solution is output to accumulator D.

In the case of multiplication between integers, address data from address register H is similarly input to registers A and B via selectors E and F, respectively.

However, in this case, as shown in Figure 4, when entering the number, the fourth
As shown in Figures (i) and (ii), without setting the multiplier abcd and the multiplicand efg, (iii) (iv)
Arrange the numbers from the top like this.

Furthermore, it is specified that the result of multiplication between integers is, for example, 7 digits, the multiplier is 4 digits, and the multiplicand is 3 digits, as shown by the circle in FIG. 4(v). Therefore, the lowest digit of the multiplication result is always placed at the T mark.

If the multiplier is 4 digits or less, for example 2 digits, 00a
Input b into register A. Similarly, when the multiplicand is three digits or less, for example, two digits, Qef is input to register B.

In this way, make sure that the lowest number in the calculation result is located at the T mark.

Next, the multiplication result (v) stored in accumulator D
The upper 7 digits are taken and returned to address register H, and the lower 7 digits (7 digits marked with an x) are truncated as before.

By adding the above-mentioned numeric instruction, integer multiplication can be performed using a conventional fixed-point multiplication circuit.

(f) 0 Effects of the Invention As described in detail above, the present invention has the great effect that integer multiplication can be performed by making simple changes to the conventional fixed-point circuit.

[Brief explanation of the drawing]

FIG. 1 shows the configuration of a multiplier section of a DSP according to the prior art. In the figure, A and B are registers, C is a multiplication circuit, and D is an accumulator. FIG. 2 is a diagram for explaining the operation of the circuit shown in FIG. 1. FIG. 3 is a diagram showing an embodiment of the present invention. In FIG. 3, E and F are selectors, G is a data memory register, H is an address register, and other symbols are the same as in FIG. FIG. 4 is a diagram for explaining the operation of FIG. 3. IJ b h 口 し し す 7 A (Ii) 口 T] = [ENG Im 工]
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Claims (1)

[Claims] a register containing the multiplier, a register containing the multiplicand,
In a fixed-point multiplication circuit consisting of a multiplication circuit and an accumulator, when performing multiplication between integers, when placing the integer multiplier and multiplicand in the register, the digit positions can be shifted so that they can be placed. A digital signal processing method characterized by: