JP3093564B2 - Multiplication device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplier, and more particularly, to a multiplier.
The present invention relates to a multiplication device that performs multiplication at high speed.

[0002]

2. Description of the Related Art Conventionally, for example, when a multiplication of a 32-digit multiplier and a 32-digit multiplicand is realized by using a multiplication circuit that performs multiplication of a 16-digit multiplier and a 32-digit multiplicand, FIG. A multiplier was used as shown.

In FIG. 5, reference numeral 401 denotes a multiplexer which selects and outputs the upper 16 digits or the lower 16 digits of the 32 digits of the multiplier. A recoding circuit 404 recodes the upper 16 digits of the multiplier output from the flip-flop (hereinafter referred to as FF) 410 or the lower 16 digits of the multiplier. 405 is a partial product addition circuit,
A partial product is created based on the multiplicand output from the recoding circuit 411 and the data output from the recoding circuit 404, and the created partial product is added to the data output from the FF 412 to obtain an intermediate result of the multiplication. Generate an intermediate product. In addition performed by the partial product addition circuit 405, addition using a redundant binary number is performed. Reference numeral 406 denotes a binary number conversion circuit, which is used to calculate the last intermediate product stored in the FF 413 and the FF 4
15 is input, and the intermediate product is converted to a binary number. Reference numeral 407 denotes an aligner for storing the intermediate product converted into a binary number in a 64-digit FF 414. The recoding circuit 404 and the partial product addition circuit 4
05 constitutes a multiplication circuit 402.

[0004] Next, the operation of the conventional multiplication device configured as described above will be described.

FIG. 6 shows FFs 410, 411, 413 and 4
14 shows data stored respectively. Here, for convenience, each cycle is denoted by C1, C2, C
3, C4.

First, in cycle C1, the lower 16 digits (XL) of the multiplier are stored in FF410, and 32 digits are stored in FF411.
The multiplicand (Y) of the digit is stored. Then, multiplication (XL · Y) is performed at the same time. At this time, the lower 16
The digit (XL) is output from the FF 410 and the recoding circuit 40
4 and input to the partial product addition circuit 405. On the other hand, the multiplicand (Y) is input from the FF 411 to the partial product addition circuit 405. At the same time, the numerical value 0 from FF412
Is input to the partial product addition circuit 405 and the partial product addition circuit 4
The addition is performed at the same time as the partial product is obtained by 05. The resulting intermediate product is stored in FFs 413 and 412 in cycle C2.

In the cycle C2, the conversion of the intermediate product ((XL.Y) rb) stored in the FF 413 into a binary number and the next multiplication (XU.Y) are performed. Where ((XL
Y) rb) indicates that (XL.Y) is represented by a redundant binary number.

In the conversion by the binary number conversion circuit 406, when the intermediate product is represented by a redundant binary number, a sequence obtained by extracting only non-positive terms is subtracted from a sequence obtained by extracting only non-negative terms. It is implemented by doing. That is, when a redundant binary number is input, the binary number conversion circuit 4
06 functions as a subtraction circuit. The binary number conversion circuit 406 functions as a 48-digit conversion circuit.

When the conversion is performed, the FF 415 outputs a numerical value 0. The output from the FF 415 is input to the binary number conversion circuit 406 as a borrow to the least significant digit of the intermediate product. When this conversion is performed, the intermediate product ((XL ·
Y) The borrowing from the 16th digit to the 17th digit from the least significant of rb) is output and stored in the FF 415 in cycle C3.

On the other hand, the upper 16 digits (XU) of the multiplier are stored in the FF 410. Then, the upper 16 digits of the multiplier (X
U) is recoded by the recoding circuit 404 and input to the partial product addition circuit 405. Partial product addition circuit 405
Is the number ((FB) rb) consisting of the 17th to the most significant digits of the intermediate product ((XL · Y) rb) stored in the FF 412 in the cycle C1, and the partial product Perform redundant binary addition with ((XU.Y) rb).

In cycle C3, a binary conversion of the intermediate product ((XU.Y + FB) rb) obtained in cycle C2 is executed. The binary number conversion circuit 406 outputs F in cycle C2.
The borrow from the 16th digit to the 17th digit from the least significant of the intermediate product ((XL.Y) rb) stored in F415 is changed to the least significant digit of the intermediate product ((XU.Y + FB) rb). Input,
A 48 digit subtraction is performed. Then, the converted result is aligned at an appropriate digit position by the aligner 407 and stored in the FF 414 in cycle C4.

[0012]

However, in the above-described conventional multiplication apparatus, when performing a 32-digit by 32-digit integer multiplication, no matter what multiplication data is input, the multiplication is always executed twice. And because the conversion is performed twice, C
An operation time corresponding to the cycle from 1 to C4 is always required.

The present invention has been made in view of the above, and an object of the present invention is to provide a multiplication device capable of increasing the speed of multiplication.

[0014]

In order to achieve the above object, the present invention detects an invalid digit higher than the most significant digit position in a multiplier at a high speed, and performs multiplication and conversion based on information on the invalid digit. By changing the number of times of execution of at least one of the above, the execution time of the multiplication is reduced.

Specifically, the solution taken by the present invention is to perform multiplication of a multiplier consisting of n digits and a multiplicand consisting of m digits, so that L of the n digits of the multiplier is used. The present invention is directed to a multiplication device including a multiplication circuit for obtaining an intermediate result of the multiplication from a partial product of a number of digits (where L ≦ n) and the multiplicand, and a conversion circuit for converting the intermediate result into a predetermined expression. , The value of the two digits for each of two adjacent digits in a number consisting of (n + 1) digits obtained by adding a digit indicating a sign to the uppermost digit of the multiplier with respect to the most significant digit of the multiplier An invalid digit setting means for calculating an exclusive OR between the two and outputting the calculation result; and detecting an invalid digit higher than the highest significant digit position in the multiplier based on the calculation result of the invalid digit setting means. High order invalid digit detection means,
The number of driving of at least one of the multiplication circuit and the conversion circuit is changed based on the information on the invalid digit of the multiplier output from the upper invalid digit detecting means. is there.

[0016]

According to the above configuration, in the multiplication device for performing multiplication of the n-digit multiplier and the m-digit multiplicand, before the multiplication is performed,
The invalid digit setting means is provided for every two adjacent digits in a number consisting of (n + 1) digits obtained by adding a digit indicating a sign to the uppermost digit of the most significant digit of the n-digit multiplier. Calculates the exclusive OR of the values. Here, the result of the exclusive OR operation between the values of the digits corresponding to the invalid digits higher than the most significant digit position in the multiplier is always 0 regardless of the value of the invalid digits. Thus, the upper invalid digit detecting means can detect the arrangement of invalid digits higher than the highest significant digit position in the multiplier. Therefore, it is possible to reduce the number of times of driving of the multiplication circuit, the conversion circuit, or the multiplication circuit and the conversion circuit based on the information on the invalid digit of the multiplier output from the upper invalid digit detection means, and to reduce the execution time of the multiplication. Can be shortened.

[0017]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a configuration of a multiplication device according to the present embodiment. Here, it is assumed that the multiplication device multiplies the 32-digit multiplier by the 32-digit multiplicand and outputs a 64-digit product.

In FIG. 1, reference numeral 201 denotes an invalid digit setting circuit. Reference numeral 202 denotes a high-order invalid digit detection circuit, which determines whether all of the high-order 16 digits of the multiplier are invalid digits. 203
Denotes a multiplexer, which selects the lower 16 digits of the multiplier at the first multiplication, and selects the upper 16 digits of the multiplier at the second multiplication. Reference numeral 204 denotes a recode circuit, and
Recode is performed for 6 digits or lower 16 digits. Also,
Reference numeral 205 denotes a partial product addition circuit that creates a partial product based on the multiplicand output from the FF 211 and data output from the recoding circuit 204, and further generates the partial product and F
An intermediate product as an intermediate result of the multiplication is generated by adding the data output from F212. For example, in addition by the partial product addition circuit 205, addition using a redundant binary number is performed. 206 is a binary number conversion circuit,
The previous intermediate product stored in 213 is input, and this intermediate product is converted into a binary number. An aligner 207 stores the converted intermediate product in a 64-digit FF 214. A sign extension circuit 208 performs sign extension on the data output from the FF 214. 209
Is a multiplexer, which selects and outputs one of the output from the sign extension circuit 208 and the output from the FF 214. 210, 211, 212, 214, 216,
217, 218 and 219 are FFs, and the clock CL
Data is taken in at the rise of K. Reference numerals 213 and 215 denote FFs controlled by the clock CLK and a control signal output from the upper-order invalid digit detection circuit 202.
In particular, the FFs 212 and 215 are FFs with reset. The recoding circuit 204 and the partial product adding circuit 205
A multiplication circuit 220 is constituted by these.

Here, the operation of the invalid digit setting circuit 201 and the upper invalid digit detecting circuit 202 will be described. Here, a case will be described in which it is determined whether the upper 16 digits of a 32-digit multiplier as a signed integer or an unsigned integer are invalid digits.

Now, if the 32-digit multiplier is a signed integer, it is expressed as in equation (1). If the 32-digit multiplier is an unsigned integer, as in equation (2). Shall be represented.

[0022] a signed integer _{Xs X 30 ···· X 1 X 0} ... (1) unsigned integer _{X 31 X 30 ···· X 1 X} 0 ... (2) In this case, the most significant significant digit position of the multiplier Is defined as follows.

If the multiplier is a signed integer, and ones continue from the most significant digit (sign digit) of the multiplier, it is considered that the sign is extended. For example, equations (3) and (4) are equivalent.

[0024] _{(Xs X 30 ···· X 1 X} 0) = (T110 ···· 00) ... (3) (Xs X 30 ···· X 1 X 0) = (00T0 ···· 00 ) (4) Here, T means minus one. That is, it may be considered as a sign digit.

In the case of Expression (3), the most significant digit position of the multiplier is one digit position higher than the digit position where a value other than 1 (including T) appears first from the most significant position. Also, depending on the multiplier, a value other than 1 (including T) may be the first digit position when viewed from the top. Therefore, when the multiplier is a signed integer and is a negative number, the most significant digit position of the multiplier is greater than the digit position where a value other than 1 (including T) appears first from the most significant position or the digit position. It is the upper digit position by one digit.

The multiplier is a signed integer, and
If 0s continue from the most significant digit (sign digit) of the multiplier,
The digit position where a value other than 0 appears first from the highest order is the highest significant digit position.

The same applies to the case where the multiplier is an unsigned integer. The digit position where a value other than 0 appears first from the highest order is the highest significant digit position.

As described above, the most significant digit position of the multiplier is, when the multiplier is a signed integer, the digit position where a value different from the value of the sign digit (Xs) appears first from the most significant position or from the digit position thereof. Is also the upper digit position by one digit. When the multiplier is an unsigned integer, the value is the digit position where the value 1 appears first when viewed from the top.

As a result, when detecting an invalid digit higher than the most significant digit position in the multiplier, the value to be detected from the most significant digit depends on whether the multiplier is a signed integer or an unsigned integer. It will be different.

Therefore, in this embodiment, the 32-digit multiplier is set to 3
Convert to a 3-digit signed integer. When the 32-digit multiplier is a 32-digit signed integer shown in equation (1), the converted 33-digit signed integer is expressed in equation (5), and the 32-digit multiplier is 32-digit shown in equation (2). Equation (6) shows the converted 33-digit signed integer in the case of the unsigned integer of.

[0031] a signed integer _{Xs Xs X 30 ···· X 1 X} 0 ... (5) unsigned integer _{0 X 31 X 30 ···· X 1} X 0 ... (6) multiplier is 32-digit signed integer In the case of, conversion to a signed integer of 33 digits can be realized by sign-extending Xs. When the multiplier is an unsigned integer, conversion to a signed integer of 33 digits can be realized by inputting a value 0 to the sign portion (the 33rd digit from the lowest order).

If the multiplier is a 32-digit signed integer, it is expanded as shown in equation (5), and if the multiplier is a 32-digit unsigned integer, it is expanded as shown in equation (6). , Since a 32-digit multiplier can be converted to a 33-digit signed integer, the most significant digit position of the multiplier is the digit position or the first digit where a value different from the value of the most significant digit in the 33-digit signed integer appears. The digit position is one digit higher than the position.

FIG. 2 shows an example of the configuration of the invalid digit setting circuit 201. In FIG. 2, an invalid digit setting circuit 201
Is an AND circuit 301 and 31 exclusive OR circuits 302
And When the multiplier is not a signed integer, the AND circuit 301 outputs the value of the 32nd digit from the lowest order of the multiplier. Each exclusive OR circuit 302 outputs information indicating that adjacent two-digit values in the multiplier are the same. Reference numeral 202 denotes a high-order invalid digit detection circuit.

The function of the AND circuit 301 will be described. As an input to the invalid digit setting circuit 201, a 32-digit multiplier is input. Here, the 32-digit multiplier is A ₃₁ A _30.
Assuming that A ₀ , the signed 33-digit integer obtained as described above is expressed as in Equation (7) when the multiplier is a signed integer of 32 digits, and the multiplier is a 32-digit signed integer. If it is an unsigned integer, it is expressed as in equation (8).

Signed integer A ₃₁ A ₃₁ A ₃₀ ... A ₀ (7) Unsigned integer 0 A ₃₁ A ₃₀ ... A ₀ (8) Most significant digit in 33-digit signed integer And whether the value of the least significant digit is the same as the value of the 32nd digit from the least significant value is obtained by calculating the exclusive OR of the value of the most significant digit and the value of the 32nd least significant digit. Can be obtained by:

When the multiplier is a signed integer, A31 exclusive OR A31 = 0 (9) When the multiplier is an unsigned integer, 0 exclusive OR A31 = A31 (10) According to Expressions (9) and (10), when the value of the most significant digit and the value of the 32nd digit from the least significant in the 33-digit signed integer are the same, the logic that the value becomes 0 is as follows: It becomes like (11).

(Sint logical product 0) logical sum ｛! (Sint) Logical product A31｝ =! (Sint) Logical product A31 (11) Here,! Indicates logical inversion, and “sint” takes a value of 1 when the multiplier is a signed integer, and takes a value of 0 when the multiplier is an unsigned integer. That is, the logic of the AND circuit 301 is configured. Therefore, AND circuit 3
01 is the exclusive of the value of the most significant digit and the value of the 32nd digit from the least significant in a 33-digit signed integer obtained by adding a digit indicating a sign to the uppermost digit of the most significant digit of the 32-digit multiplier. Circuit that calculates the logical OR, and implements a function of outputting information that the value of the most significant digit and the value of the 32nd digit from the least significant in a 33-digit signed integer are the same. ing.

As described above, the invalid digit setting circuit 2 of the present embodiment
When 01 is used, the value 0 can be set to all invalid digits higher than the highest significant digit position in the multiplier by exclusive OR and simple logic between two adjacent digits in the multiplier. .

In this embodiment, all data can be input to the upper invalid digit detecting circuit 202 in a predetermined time regardless of the number of digits of the multiplier.

Now, the invalid digit setting circuit 201 as described above
And how the multiplication is executed using the upper invalid digit detection circuit 202 will be described.

First, a case will be described in which the invalid digit setting circuit 201 and the high-order invalid digit detection circuit 202 determine that there are digits other than invalid digits in the upper 16 digits of the multiplier.

FIG. 3 shows the operation in this case.
0, 211, 213 and 214 are shown respectively. Here, for convenience, each cycle will be referred to as C1, C2, C3, and C4, respectively.

In cycle C1, the lower 16 digits of the multiplier (X
L) multiplied by a 32-digit multiplicand (Y), and the top one of the multiplier
A determination is made as to whether all six digits (XU) are invalid digits. If there is a digit other than the invalid digit in the upper 16 digits (XU) of the multiplier, the upper invalid digit detecting circuit 202 outputs the value 0.
Is output. Thus, the FFs 213 and 215 are activated by the clock CLK. In the multiplexer 209, the output from the FF 214 is selected.

The lower 16 digits of the multiplier (XL) are stored in the FF 210.
Is stored, and a 32-digit multiplicand (Y) is stored in the FF 211. At this time, the lower 16 digits (XL) of the multiplier output from the FF 210 are recoded by the recoding circuit 204 and input to the partial product addition circuit 205. On the other hand, 32
The digit multiplicand (Y) is obtained from the FF 211 by the partial product addition circuit 20.
5 is input. At the same time, the numerical value 0 is input from the FF 212, and the addition is performed simultaneously with the partial product in the partial product addition circuit 205. The resulting intermediate product is FF213
And FF212 in cycle C2.

In cycle C2, the intermediate product obtained in cycle C1 is stored in FF213 and FF212.
The intermediate product ((XL.Y) rb) stored in 13 is converted to a binary number and the next multiplication (XU.Y) is performed. When the intermediate product is represented by a redundant binary number, the conversion by the binary number conversion circuit 206 is performed by subtracting a sequence obtained by extracting only non-positive terms from a sequence obtained by extracting only non-negative terms from the intermediate product. Will be implemented. That is, when a redundant binary number is input, the binary number conversion circuit 206 functions as a subtraction circuit. The binary number conversion circuit 206 functions as a 48-digit conversion circuit. At this time, a numerical value 0 is output from the FF 215. The output from the FF 215 is input to the binary conversion circuit 206 as a borrow to the least significant digit of the intermediate product. When this conversion is executed, the intermediate product ((XL.Y)
The borrow from the 16th digit to the 17th digit from the lowest order of rb) is output and stored in the FF 215 in cycle C3.

On the other hand, the upper 16 digits (XU) of the multiplier are stored in the FF 210. Then, the upper 16 digits of the multiplier (X
U) is recoded by the recoding circuit 204 and input to the partial product addition circuit 205. Partial product addition circuit 205
Is the number ((FB) rb) consisting of the seventeenth digit from the least significant digit to the most significant digit of the intermediate product (XL.Y) obtained in cycle C1, and the partial product ((XU.Y) rb) ) Is performed.

In cycle C3, a binary conversion of the intermediate product ((XU.Y + FB) rb) obtained in cycle C2 is performed. The binary number conversion circuit 206 borrows the intermediate product ((XL.Y) rb) stored in the cycle C2 from the 16th digit to the 17th digit from the least significant bit ((XU.
Y + FB) rb) is input to the least significant digit, and 48 digits are subtracted. The converted result is stored in the aligner 20.
7 and is stored in the FF 214 after being aligned to an appropriate digit position.

In the cycle C4, the result stored in the FF 214 is selected and output by the multiplexer 209.

As described above, when there are digits other than invalid digits in the upper 16 digits of the multiplier, four cycles are always required to realize multiplication.

Next, a case will be described in which the invalid digit setting circuit 201 and the high-order invalid digit detection circuit 202 determine that all of the upper 16 digits of the multiplier are invalid digits.

FIG. 4 shows the operation in this case.
0, 211, 213 and 214 are shown respectively. Again, for convenience, each cycle will be referred to as C1, C2, C3, respectively.

In cycle C1, the lower 16 digits of the multiplier (X
L) multiplied by a 32-digit multiplicand (Y), and the top one of the multiplier
A determination is made as to whether all six digits (XU) are invalid digits. When all of the upper 16 digits (XU) of the multiplier are invalid digits, a value 1 is output from the upper invalid digit detection circuit 202. Further, multiplication of the lower 16 digits (XL) of the multiplier and the 32-digit multiplicand (Y) is performed.

In cycle C2, a binary conversion of the intermediate product ((XL.Y) rb) obtained in cycle C1 is executed.
A conversion result of 48 digits is obtained. At the same time, the top 16
Multiplication of the digit (XU) by the 32-digit multiplicand (Y) is also performed.

In cycle C3, the value of the conversion result is FF2
14 and expanded from 48 digits to 64 digits by the sign extension circuit 208 and output. At this time, the output of the sign extension circuit 208 is selected and output by the multiplexer 209. The intermediate product obtained in cycle C2 is FF
The value output from the binary number conversion circuit 206 is constant because the FF 215 does not operate without being taken into the 213.

As described above, when all the upper 16 digits of the multiplier are invalid digits, the multiplication is completed in three cycles.

Therefore, according to the present embodiment, the execution time of the multiplication can be reduced by using the invalid digit setting circuit 201 and the upper invalid digit detecting circuit 202.

In the present embodiment, it is determined whether or not all the upper 16 digits of the multiplier are invalid digits. However, the number of digits can be changed according to the multiplication circuit 220 used.

Further, the multiplying device according to the present embodiment uses the binary conversion circuit 2 based on the output from the upper significant digit detecting means 202.
06 is configured to change the number of driving,
The number of times of driving of the multiplication circuit 220 or the number of times of driving of the multiplication circuit 220 and the binary number conversion circuit 206 may be changed based on the output from the upper-order invalid digit detection circuit 202.

[0059]

As described above, according to the multiplication apparatus according to the present invention, a number consisting of (n + 1) digits obtained by adding a sign indicating a sign above the most significant digit of a multiplier of n digits The exclusive OR of the values of the two digits is calculated for each of the two digits adjacent to each other in.
An arrangement of invalid digits higher than the most significant digit position in the multiplier can be detected. Therefore, the number of times of driving of at least one of the multiplication circuit and the conversion circuit can be reduced based on the information on the invalid digit of the multiplier, so that the speed of multiplication can be increased.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a multiplication device according to one embodiment of the present invention.

FIG. 2 is a logic circuit diagram showing a configuration of an invalid digit setting circuit of the multiplication device.

FIG. 3 is a timing chart showing the operation of the multiplication device when there are digits other than invalid digits in the upper 16 digits of the multiplier.

FIG. 4 is a timing chart showing an operation of the multiplication device when all 16 high-order digits of a multiplier are invalid digits.

FIG. 5 is a block diagram showing a configuration of a conventional multiplication device.

FIG. 6 is a timing chart showing the operation of the conventional multiplication device.

[Explanation of symbols]

 Reference Signs List 201 invalid digit setting circuit 202 upper invalid digit detection circuit 203, 209 multiplexer 204 recode circuit 205 partial product addition circuit 206 binary conversion circuit 207 aligner 208 sign extension circuit 210-219 flip-flop (FF) 220 multiplication circuit

Claims (1)

(57) [Claims] To perform multiplication of a multiplier consisting of n digits and a multiplicand consisting of m digits, L digits out of n digits of the multiplier (where L ≦ n) A multiplication circuit that obtains an intermediate result of the multiplication from a partial product of the number consisting of the multiplicand and a conversion circuit that converts the intermediate result into a predetermined expression. For every two adjacent digits in a number consisting of (n + 1) digits obtained by adding a digit indicating a sign to the upper part of the most significant digit, exclusive OR of the values of the two digits is calculated. An invalid digit setting unit that outputs a calculation result; and a high-order invalid digit detection unit that detects an invalid digit higher than the most significant digit position in the multiplier based on the calculation result of the invalid digit setting unit. The invalid digit of the multiplier output from the upper That based on the information, the multiplication apparatus characterized by being configured to vary the driving frequency of the at least one circuit of said multiplier circuit and conversion circuit.