JP4643951B2 - CONVERTING DEVICE AND CONVERTING METHOD FOR CONVERTING RESIDUAL CONVERSION NUMBER TO BINARY NUMBER - Google Patents

Description

  The present invention relates to a conversion apparatus and a conversion method for converting a converted number of a residue system into a binary number. In particular, the present invention relates to a conversion apparatus and a conversion method for converting a residue conversion number that performs high-speed conversion with a small amount of hardware into a binary number.

  Conventionally, a numerical operation by a digital circuit is realized by a logic circuit based on a binary number. In recent years, a numerical calculation method using a residue number system (RNS) has been proposed (Non-Patent Document 1). It is known that addition, subtraction, and multiplication by a residue system can be performed at a higher speed than conventional binary arithmetic operations for the following reason.

  In addition in binary numbers, a carry signal is generated from the operation of each bit and further propagates from the LSB side to the MSB side. For this reason, until the carry of the (i-1) th bit arrives. The calculation result of the i-th digit cannot be determined. Therefore, the amount of delay increases in proportion to the number of bits of the operand to be operated. On the other hand, computation by the residue system can be performed in parallel independently for each residue digit, and the computation speed does not depend on the number of computation bits, so that it can be speeded up.

  In the remainder system, one numerical value X is expressed by a combination of N remainder numbers (residue values).

Equation _{(1-1) x i = X mod} m i in a (x _i = | | X _mi also expressed), X i-th modulus: in (modulus modulus) modulo divided by m _i (Residue) is there. Further, the remainder digits of x _i (Residue Digit), or, also referred to as a remainder value by the modulus m _i. Here, mod is an abbreviation for modulo, and means that the following equation (1-2) is established.

Where p is the quotient obtained by dividing the X in the m _i. This time is called the X and x _i are congruent (congruent) for modulus m _i, may be expressed by the following equation using a congruence (congruence).

When N moduli m _i (i = 0,1,2, ..., N-1) are relatively prime, all numerical values X in the range shown below are uniquely assigned to N remainder numbers. Can be expressed in a specific combination. At this time, {m ₀ , m ₁ , m ₂ ,..., _{M N−1} } is called a modulus set.

As an example, consider the remainder representation using the modulus set {m ₀ , m ₁ , m ₂ , m ₃ } = {8,7,5,3}. In this remainder system, M = 8 × 7 × 5 × 3 = 840 integers can be represented. For example, (0,0,0,0) _RNS is 0 or 840 or 1680 ..., (1,1,1,1) _RNS is 1 or 841 or 1681 ..., (0,1,3,2) _RNS is 8 Or 848 or 1688 ..., (0,1,4,1) _RNS is 64 or 904 or 1744 ... In the case of the modulus set {8, 7, 5, 3}, the number of bits necessary to express each remainder digit is [3 bits, 3 bits, 3 bits, 2 bits] = 11 bits.

  In the remainder system, addition, subtraction, and multiplication can be realized by independently calculating each remainder digit, and propagation of information between the remainder digits is not necessary. That is, the following theorem holds.

(Theoretical addition and subtraction theorem)
The operator “◯” is an operator expressing addition, subtraction, or multiplication, the modulus of the remainder system is {m ₀ , m ₁ ,..., _{M N-1} }, and the operand is A = (a ₀ , a ₁ , a ₂ , ..., a _N-1 ), B = (b ₀ , b ₁ , b ₂ , ..., b _N-1 ), Z = A〇B is the remainder for each modulus of the operand This can be realized by calculating between digits.

Here, the left side is the remainder value by m _i of Y. In addition, the calculation according to the expression (1-5) is referred to as residue addition, residue subtraction, or residue multiplication. The theorem of remainder addition / subtraction multiplication is proved as shown below.

(Proof of the theorem of remainder addition and subtraction)
From the definition of the numerical expression of the residue system, the following expression (1-6) is established.

Here, p _i is the quotient obtained by dividing A by modulus m _i, q _i is the quotient obtained by dividing B by the modulus m _i.

  In addition / subtraction, the following formula (1-7) is established.

Here, from (p _i + q _i ) m _i ≡0, the following expression (1-8) is established.

  On the other hand, in the multiplication, the following expression (1-9) is established.

Here, from (p _i q _i m _i + p _i b _i + q _i a _i ) m _i ≡0, the following expression (1-10) is established.

  From the above formulas (1-8) and (1-10), it can be seen that each remainder digit of Y can be calculated by computing each remainder digit of A and B. Therefore, it is proved that the theorem of the equation (1-5) holds.

  According to the residue system addition / subtraction theorem, the addition / subtraction multiplication in the residue system is a residue that performs an operation on the corresponding residue digit for each of the two operand digits A and B that are input and the corresponding operation result Y that is output. This can be realized by providing an arithmetic ALU (Arithmetic Logic Unit). And the calculation of a certain remainder digit can be performed independently of the calculation of other remainder digits. In the calculation in the remainder calculation ALU corresponding to each remainder digit, the delay due to carry propagation can be limited to the number of bits of the remainder digit, so that the calculation can be performed at higher speed.

  In order to speed up the numerical operation using the residue system, the binary system or the decimal system is converted to the residue system (Binary-to-Residue (B / R) converter), and the residue system is converted to the binary system or A conversion to a decimal system (Residue-to-Binary (R / B) converter) is required. The B / R converter can be realized relatively easily, and several methods for realizing the R / B converter have been studied.

As an R / B converter, one using the Chinese Remainder Theorem is common. When the modulus set is {m ₀ , m ₁ , m ₂ , m ₃ } = {8,7,5,3}, Y = (y ₀ , y ₁ , y ₂ , y ₃ ) = (5,3 , 4,2) is converted to a decimal number as an example.
(5,3,4,2) can be modified as shown in the following formula (1-11) from the remainder system addition / subtraction theorem shown in formula (1-5), and formula (1-12) Obtainable.

Thus, the decimal representation corresponding to (1,0,0,0), (0,1,0,0), (0,0,1,0), (0,0,0,1) If it is obtained in advance, an arbitrary remainder expression (y ₀ , y ₁ , y ₂ , y ₃ ) can be converted into a decimal number expression using the following equation (1-13).

Here, (1,0,0,0) is the remainder for the modulus 8 (= m ₀ ) and the modulus subset {7,5,3} = {m ₁ , m ₂ , m ₃ } It is a numerical value whose remainder is 0. The latter condition can be satisfied by calculating (1,0,0,0) on condition that it is the least common multiple of m ₁ , m ₂ , and m ₃ . These conditions can be represented by the following formula (1-14).

Here, β0 is a natural number. If m ₁ , m ₂ , and m ₃ are relatively prime, the conditions a) and b) can be rewritten to the following expression (1-15) from the expression (1-4).

By obtaining the above natural number β ₀ , a decimal number representation of (1,0,0,0) can be obtained. The following is (1,0,0,0), (0,1,0,0), (0,0,1,0), (0,0, Indicates the decimal representation of (0,1).

The conversion of the numerical value (5,3,4,2) expressed in the {8,7,5,3} residue system into the decimal number from the expression (1-16) is 5 × 105 + 3 × 120 + 4. × 336 + 2 × 280 = 2117 However, since the numerical value that can be expressed in this remainder system is 0 ≦ Y <M = 840, Y = | 2117 | _M = 437.

  In general, the Chinese remainder theorem is given by

Here, β _i · (M / m _i ) is called a multiplicative inverse (hereinafter simply “inverse”) in the Chinese remainder theorem.

When the Chinese remainder theorem is used as it is, it is necessary to multiply each remainder digit y _i by a constant β _i · (M / m _i ) as shown in the equation (1-17), which requires calculation time. . For this reason, the merit (computation speed improvement) of multiplying by a remainder system is remarkably impaired.

  In order to solve this problem, a method of calculating a Chinese remainder theorem at high speed using a small circuit by selecting a specific modulus set has been disclosed (see Non-Patent Document 2).

In Non-Patent Document 2, the modulus set is defined as follows.

However, k is an integer greater than or equal to 0, p is a natural number. For example, when p = 3 and k = 1, S _k = {7, 9, 65}. From Expression (1-4), the number M of numerical values that can be expressed by the remainder system of Expression (1-18) is expressed by Expression (1-19) below.

In order to apply the Chinese remainder theorem to the modulus set S _k, β _i satisfying the condition of b) in equation (1-14) is obtained, and the reciprocal is determined.

(1) About m ₀ (= 2 ^p −1) From the expressions (1-4) and (1-18), the following expression (1-20) is obtained.

Here, since 2 ^p mod m ₀ = 1 from the expression (1-18), the expression (1-20) can be transformed into the following expression (1-21).

Furthermore, when the condition of a) in the formula (1-14) is applied, the formula (1-21) can be transformed into the following formula (1-22).

Therefore, when the modulus set of Expression (1-18) is used, the following Expression (1-23) is established.

(2) m _i (= 2 ^ (2 ^i-1 p) +1, where i> 0) From the condition of b) in equation (1-14) and equation (1-18), 1-24) is established.

この変形においては、式（１−１８）により導かれる式2^(2^i-1p) mod m_i = -1をもちいた。 Here, the part A in the formula (1-24) is represented by the following formula (1-25).

In this modification, the formula 2 ^ (2 ^i-1 p) mod m _i = -1 derived from the formula (1-18) was used.

On the other hand, the portion B in the formula (1-24) is represented by the following formula (1-26).

Therefore, Formula (1-24) can be transformed into the following Formula (1-27) by Formulas (1-25) and (1-26).

If the formula (1-27) is congruent with 1, the condition of the formula (1-14) a) and the formula (1-18) are satisfied. Therefore, when β _i (−2 ^{k−i + 2} ) ≡1 mod m _i is solved for β _i , the following equation (1-28) is obtained.

By substituting Equations (1-23) and (1-28) shown above into Equation (1-17), the Chinese remainder theorem for the modulus set shown in Equation (1-18) is Equation (1-29) is obtained.

Next, a specific calculation example of Expression (1-29) is shown as S _k = {m ₀ , m ₁ , m ₂ } = {7, 9, 65}.
In this example, since k = 1, the expression (1-29) becomes the following expression (1-30).

When formula (1-30) is expanded and arranged, formula (1-31) is obtained.

Since the reciprocal number of each term in the formula (1-31) is a power of 2, it can be realized by a binary bit shift operation. From this, each term of Formula (1-31) can be calculated only by addition / subtraction of y ₀ and y ₁ and addition / subtraction of y ₂ . Even when k ≧ 2, the same modification as that of the expression (1-31) is possible. Therefore, by using the technique of Non-Patent Document 2, the calculation of the Chinese remainder theorem, which conventionally required multiplication and addition, can be realized only by addition and subtraction. As a result, when the Chinese remainder theorem is implemented in hardware, the circuit area can be reduced and the calculation time can be shortened.
B. Parhami, Computer Arithmetic, Oxford University Press, 2000, pp. 54-72 W. Wang, MNS Swamy, MO Ahmad, Y. Wang, "A Parallel Residue-to-Binary Converter," in Proc. IEEE Inte. Conf. Acoustics, Speech, ad Signal Processing, Phenix, AZ, March 1999, pp.1541-1544

In Non-Patent Document 2, an adder and / or subtracter of about 4 · 2 ^k pk bits is required for the calculation of Equation (1-31). For example, when k = 1 and p = 3, a p-bit adder is required for the calculation of (y ₀ + y ₁ ) and (y ₀ −y ₁ ), and 4 · 2 ^k p is required to add y ₂ A bit adder is required. Since this addition is repeated (modulus number-1) times (= k times), a total of about ^4.2k p bits of adders are required.

  Therefore, an object of the present invention is to provide a conversion device and a conversion method that can solve the above-described problems. This object is achieved by a combination of features described in the independent claims. The dependent claims define further advantageous specific examples of the present invention.

  According to the first aspect of the present invention, there is provided a conversion device that converts a number to be converted expressed by a residue system into a binary number, wherein the residue system is a plurality obtained by dividing the number to be converted by each of a plurality of moduli. The converted number is expressed by a set of remainder values of the following: the first modulus is a power value greater than the product of the modulus less than the first modulus, which is a power of 2 by a natural number, and 1 For each of a plurality of moduli, a conversion value corresponding to a modulus corresponding to the modulus, which is a binary value based on a value obtained by multiplying the remainder of the modulus by a product of a modulus other than the modulus. A partial bit string generation unit that generates a partial bit string included in at least a part of the plurality of moduli, A conversion value addition unit corresponding to a modulus for calculating the binary converted number obtained by adding the conversion values corresponding to the moduli for each of the plurality of moduli, and the conversion value addition unit corresponding to the modulus A lower-order bit string of a predetermined number of bits included in a part of the first partial sum that is the sum of the modulus-corresponding conversion values corresponding to at least one of the moduli smaller than the first modulus is higher than the lower-order bit string A lower bit string duplicating unit that replicates as an upper bit string of digits and generates an added number including the same upper bit string and lower bit string, and adds the partial bit string corresponding to the first modulus to the added number; At least one of the second partial sums obtained by adding the modulus corresponding conversion value for the first modulus to the first partial sum. Which provides a conversion device having a bit sequence adder for calculating a low-order bit string included in.

  The minimum modulus is a natural number of 2 or more obtained by subtracting 1 from a power value of a natural number of 2, and each of the non-minimum moduli of the plurality of moduli is smaller than the modulus that is a power of 2 by a natural number. A value obtained by adding 1 to a power value greater than the product of the moduli, and the lower bit string duplicating unit, for each of the non-minimum moduli of the plurality of moduli, corresponds to all the moduli smaller than the moduli. A lower bit string having a predetermined number of bits included in a part of the first partial sum, which is the sum of the conversion values corresponding to the modulus, is copied as an upper bit string having a higher digit than the lower bit string, and the subject for the modulus is copied. An addition number is generated, and the bit string addition unit generates a maximum of the plurality of moduli. For each of the moduli that is not, the first bit obtained by adding the partial bit string corresponding to the modulus to the addend number for the modulus and adding the modulus corresponding conversion value for the modulus to the first partial sum. A lower bit string included in at least a part of the two-part sum may be calculated.

ただし、kは0以上の整数であり、pは自然数である。 The plurality of moduli take the values shown in the following equation 32, and the lower bit string duplicating unit, for each of the non-minimum moduli m _i (i = 1,..., K + 1) among the plurality of moduli, The lower bit string of p · 2 ⁱ⁻¹ bits in the first partial sum, which is the sum of the modulus-corresponding conversion values corresponding to all moduli smaller than the modulus m _i , is assigned to the upper digit p · 2 ^{i of the} lower bit string. ^-1 bit as a high-order bit string to generate the p · 2 ⁱ bit added number, and the bit string adding unit is configured to generate the non-minimum modulus m _i (i = 1,... for k + 1) respectively, to said augend for the modulus m _i, and adding the partial bit string of the lower p · 2 ⁱ bits in the modulus corresponding conversion value corresponding to the modulus m _i, the first 1 copy The modulus corresponding conversion value for the modulus may be calculated lower bit string of p · 2 ⁱ bits in the second partial sum plus the sum.

However, k is an integer greater than or equal to 0, and p is a natural number.

The bit string adding unit, for the first modulus m _i1, said p · 2 ⁱ¹ bit augend, the p · 2 ⁱ¹ bits for adding the partial bit string of p · 2 ⁱ¹ bits in the modulus corresponding conversion value an adder, a second of said modulus m _i2, p · 2 ⁱ² of bits of the in augend, the addition of p · 2 ⁱ² bits for adding the partial bit string of p · 2 ⁱ² bits in the modulus corresponding conversion value May also be included.

  The bit string adding unit, when the addition causes an overflow exceeding the number of bits to be added and the number of bits of the partial bit string, a lower bit string having the same number of bits as the number to be added in the bit string obtained as a result of the addition The lower bit string of the second partial sum may be calculated by adding the bits overflowing to the lower bits of.

  According to a second aspect of the present invention, there is provided a conversion device for converting a converted number expressed by a residue system into a binary number, wherein the residue system is a plurality of divisions obtained by dividing the converted number by each of a plurality of moduli. The converted number is expressed by a set of remainder values of the following: the first modulus is a power value greater than the product of the modulus less than the first modulus, which is a power of 2 by a natural number, and 1 For each of a plurality of moduli, a modulus-corresponding conversion that is a binary value corresponding to the modulus based on a value obtained by multiplying the remainder of the modulus by a product of a modulus other than the modulus A modulus-corresponding conversion value generation unit for generating a value, and adding the modulus-corresponding conversion value for each of the plurality of moduli A modulus-corresponding conversion value adding unit that calculates the number of conversions, and the modulus-corresponding conversion value generation unit is based on a bit string of a remainder value obtained by dividing the conversion number by a second modulus smaller than the first modulus. A partial bit string generation unit that generates a partial bit string that is a part of the modulus-corresponding conversion value corresponding to the second modulus, and the partial bit string at a plurality of locations of the modulus-corresponding conversion value corresponding to the second modulus. There is provided a conversion device including a partial bit string duplicating unit that generates a conversion value corresponding to a modulus obtained by duplicating the partial bit string and the first modulus.

  The minimum modulus is a natural number of 2 or more obtained by subtracting 1 from a power value of a natural number of 2, and each of the non-minimum moduli of the plurality of moduli is smaller than the modulus that is a power of 2 by a natural number. The partial bit string generation unit takes a value obtained by adding 1 to a power value greater than the product of the moduli, and for each non-minimum modulus among a plurality of moduli, the partial bit string generation unit calculates a remainder value by the moduli of the number to be converted. The partial bit string may be generated by subtracting the remainder value from the value shifted to the upper digit side by the number of bits corresponding to the natural number.

ただし、kは0以上の整数であり、pは自然数である。 The plurality of moduli takes the values shown in the following Equation 33, and the partial bit string generation unit is configured to calculate the non-minimum moduli m _i (i = 1,..., K + 1) among the plurality of moduli. Generating the partial bit string of 2 ⁱ · p bits by subtracting the remainder value from the value obtained by shifting the remainder value by the modulus m _i of the number to be converted to the upper digit side by 2 ⁱ⁻¹ · p bits, and generating the partial bit string replication section replicates for each of the moduli m _i not the minimum and maximum of the plurality of modulus, at a plurality of locations of the modulus corresponding conversion value corresponding to the modulus m _i, the partial bit string by 2 ⁱ · p bit interval by may generate the modulus corresponding conversion value corresponding to the modulus m _i.

However, k is an integer greater than or equal to 0, and p is a natural number.

The modulus corresponding conversion value generating unit, for the first modulus m _i1, on the basis of the remainder value by said first modulus m _i1 of the number of conversions to generate a first of said partial bit string of the 2 ⁱ¹ · p bits For the first partial bit string generation unit and the second modulus m _i2 , a second partial bit string of 2 ⁱ² · p bits is generated based on a remainder value of the number to be converted by the first modulus m _i2 The second partial bit string generation unit that performs the first partial bit string to generate the modulus-corresponding conversion value corresponding to the modulus m _i1 by duplicating the first partial bit string at intervals of 2 ⁱ¹ · p bits. by duplicating the bit string replication unit, the second partial bit string by 2 ⁱ² · p bit interval, a second of said partial bit double generating the modulus corresponding conversion value corresponding to the modulus m _i2 It may have a part.

  According to a third aspect of the present invention, there is provided a conversion method for converting a converted number expressed by a residue system into a binary number by a conversion device, wherein the residue system converts the converted number by each of a plurality of moduli. The converted number is expressed by a set of a plurality of remainder values divided, and the first modulus is a power value larger than the product of the modulus less than the first modulus obtained by raising 2 by a natural number. A modulus corresponding to the modulus, which is a binary value based on a value obtained by adding 1 and multiplying the remainder of the modulus by a product of a modulus other than the modulus for each of a plurality of moduli A partial bit string generation stage for generating a partial bit string included in at least a part of the corresponding conversion value, and each of the plurality of moduli. A modulus-corresponding conversion value adding step of calculating a binary converted number by adding the modulus-corresponding conversion value for each of the plurality of moduli based on the partial bit string In the adding step, a lower-order bit string having a predetermined number of bits included in a part of a first partial sum that is a sum of the modulus-corresponding conversion values corresponding to at least one modulus smaller than the first modulus A lower bit string duplicating step for generating an added number including the same upper bit string and lower bit string as a higher bit string having a higher digit than the bit string, and adding the partial bit string corresponding to the first modulus to the added number Then, the first partial sum is added with the modulus corresponding conversion value for the first modulus. To provide a conversion method and a bit sequence summing calculating a low-order bit string included in at least part of the partial sums.

  According to a fourth aspect of the present invention, there is provided a conversion method for converting a converted number represented by a residue system into a conversion device binary number, wherein the remainder system divides the converted number by each of a plurality of moduli. In addition, the converted number is expressed by a set of a plurality of residue values, and the first modulus is a power value larger than the product of the modulus less than the first modulus, which is a power of 2 by a natural number, 1 is added, and for each of a plurality of moduli, a modulus that is a binary value corresponding to the modulus based on a value obtained by multiplying the remainder of the modulus by a product of a modulus other than the modulus A modulus-corresponding conversion value generation stage for generating a corresponding conversion value, and adding the modulus-corresponding conversion values for each of the plurality of moduli A modulus-corresponding conversion value adding step for calculating the binary converted number, wherein the modulus-corresponding conversion value generating step divides the converted number by a second modulus smaller than the first modulus. A partial bit string generation stage for generating a partial bit string that becomes a part of the modulus-corresponding conversion value corresponding to the second modulus, and a plurality of places corresponding to the modulus-corresponding conversion value corresponding to the second modulus. There is provided a conversion method including a partial bit string duplication step of generating a conversion value corresponding to a modulus obtained by multiplying the partial bit string by the first modulus by duplicating the partial bit string.

  According to a fifth aspect of the present invention, there is provided a program for converting a converted number expressed by a remainder system into a binary number by a computer, wherein the remainder system divides the converted number by each of a plurality of moduli. The converted number is expressed by a set of a plurality of remainder values, and the first modulus is a power value larger than the product of the modulus less than the first modulus obtained by raising 2 to a power of a natural number, and 1 The program is a binary value based on a value obtained by multiplying the remainder of the modulus by a product of a modulus other than the modulus for each of a plurality of moduli. A partial bit string generator that generates a partial bit string included in at least a part of the modulus-corresponding conversion value corresponding to the modulus. And a modulus-corresponding conversion value adding unit that calculates the binary converted number by adding the modulus-corresponding conversion value for each of the plurality of moduli based on the partial bit string for each of the plurality of moduli The modulus-corresponding conversion value adding unit is included in a part of a first partial sum that is a sum of the modulus-corresponding conversion values corresponding to at least one of the moduli smaller than the first modulus. A lower bit string replicating unit that replicates a lower bit string of the number of bits as an upper bit string of an upper digit than the lower bit string, and generates an added number including the same upper bit string and lower bit string; and The partial bit string corresponding to the modulus is added to the first partial sum to the first modulus. Providing have been the modulus corresponding is converted value as it has a bit string adder for calculating a low-order bit string included in at least part of the second partial sum plus program.

  According to a sixth aspect of the present invention, there is provided a program for converting a converted number expressed by a residue system into a binary number by a computer, wherein the residue system divides the converted number by each of a plurality of moduli. The converted number is expressed by a set of a plurality of remainder values, and the first modulus is a power value larger than the product of the modulus less than the first modulus obtained by raising 2 to a power of a natural number, and 1 For each of a plurality of moduli, the program corresponds to the modulus based on a value obtained by multiplying the remainder of the modulus by a product of a modulus other than the modulus. A modulus-corresponding conversion value generating unit that generates a modulus-corresponding conversion value that is a binary value; Each of the modulus-corresponding conversion values is added to function as a modulus-corresponding conversion value adding unit that calculates the binary converted number, and the modulus-corresponding conversion value generating unit is smaller than the first modulus. A partial bit string generation unit that generates a partial bit string that is a part of the modulus-corresponding conversion value corresponding to the second modulus, based on a bit string of a remainder value obtained by dividing the number to be converted by a second modulus; A partial bit string duplicating unit that replicates the partial bit string at a plurality of locations of the modulus-corresponding conversion value corresponding to the modulus to generate the modulus-corresponding conversion value obtained by multiplying the partial bit string by the first modulus. Provide a program.

  According to a seventh aspect of the present invention, there is provided a computer-readable recording medium on which the above program is recorded.

  The above summary of the invention does not enumerate all the necessary features of the present invention, and sub-combinations of these feature groups can also be the invention.

  According to the present invention, it is possible to convert a numerical value of a residue system into a binary number at a high speed with a small amount of hardware.

  Hereinafter, the present invention will be described through embodiments of the invention. However, the following embodiments do not limit the invention according to the scope of claims, and all combinations of features described in the embodiments are included. It is not necessarily essential for the solution of the invention.

  Below, the principle of the converter (R / B converter) which converts from a remainder system to a binary number system in this embodiment is shown.

(1) The nature of the Chinese remainder theorem for the modulus set of equation (1-18) In the Chinese remainder theorem for the modulus set of equation (1-18), the inverse β _i · ( The bit string of the binary representation of M / m _i ) has the following two properties. In the following, numerical values are expressed by bit strings, but a plurality of bits may be collectively regarded as one digit.

(1a) Property 1: In the case of reciprocal circulation • β ₀ · (M / m ₀ ) In the case of β ₀ · (M / m ₀ ), the following equation (2-1a) is established.

That is, (2 ^ (2 ⁰ p) +1) becomes 1 × (2 ^ (2 ⁰ p) +1) = “00 ... 01 (p bits)” × (2 ^ (2 ⁰ p) +1 ), The p-bit bit string "00 ... 01" with the least significant bit set to "1" and the other bits set to "0" is shifted to the upper digit side by the lower p bits and p bits. It can be seen that the 2p-bit bit string “00... 0100... 01” (the 0th bit (least significant bit) and the pth bit is “1” and the other bits are “0”) duplicated in the part.

Similarly, if the above 2p bit string "00 ... 0100 ... 01" is multiplied by (2 ^ (2 ¹ p) +1), the 2p bit string will be converted into the lower 2p bits and the upper digits for 2p bits. It can be seen that the 4p-bit bit string "00 ... 0100 ... 0100 ... 0100 ... 01" replicated in the shifted 2p-bit part. This bit string is a bit string obtained by duplicating the p-bit bit string “00... 01” having the least significant bit “1” and the other bits “0” in four places, in other words, four bit strings of the p-bit. It is a combined bit string.

Similarly, (2 ^ (2 ² p) +1), (2 ^ (2 ³ p) +1), ..., (2 ^ (2 ^k p) +1) This is a 2 ^{k + 1} p-bit bit string that is a cyclic copy of the p-bit bit string “00… 01” with the lower bit “1” and the other bits “0” cyclically at 2 ^{k + 1} locations. I understand that. In other words, it is a bit string obtained by combining 2 p ^{+ 1} bit strings of the p bits.

Then, the value obtained by multiplying the 2 ^{k + 1} p-bit bit string by 2 ^{p- (k + 1)} is ^{p- (k + 1)} bits in the lower digits of the 2 ^{k + 1} p-bit bit string. By adding “0”, the bit string is shifted to the upper digit side by p− (k + 1) bits.

・ In the case of β _i・ (M / m _i ) (1 ≦ i ≦ k + 1)
In the case of β ₁ · (M / m ₁ ), the following equation (2-1b) is established.

That is, if (2 ^p -1) is regarded as a 2p-bit bit string "00 ... 0011 ... 11" in which the upper p bits are "0" and the lower p bits are "1", this value becomes (2 ^ (2 ¹ The value obtained by multiplying p) +1) is a 4p-bit bit string “00… 0011… 1100 ... which is a copy of the 2p-bit bit string and the 2p-bit part shifted to the upper digit side by 2p bits. ... 11 ”(0th bit (least significant bit) to the (p-1) th bit, 2nd bit to the 3rd p-1 bit are" 1 ", and the others are" 0 ").

Hereinafter, (2 ^ (2 ² p) +1), (2 ^ (2 ³ p) +1), ..., (2 ^ (2 ^k p), as in the case of β ₀ (M / m ₀ ) ) +1) in order, 2 ^{k + 1,} which is a duplicate of a 2 p-bit bit sequence “00… 0011… 11” with the upper p bits being “0” and the lower p bits being “1” at 2 ^k locations. It can be seen that the bit string is p bits. In other words, it is a bit string ^{obtained by} combining 2 ^k bit strings of the 2p bits.

Similarly to the case of β ₀ · (M / m ₀ ), the value obtained by multiplying the bit string of 2 ^{k + 1} p bits by 2 ^{p- (k + 1)} is 2 ^{k + 1} p By adding p- (k + 1) “0” s to the lower digits of the bit sequence of bits, the bit sequence is shifted to the upper digits by p- (k + 1) bits.

Also, if regarded as a combination of (2 ^p -1) of 2 ^p and -1, (2 ^p -1) is the p-th bit is "1", the 0th bit is "-1", and the other bits Can be regarded as a 2p-bit bit string "00 ... 0100 ... 0 (-1)". Here, in the expression (2-1b), (-1) in the complement of 1 is represented by “1” with a hyphen. If this expression format is used, the least significant bit is “1” in the part of (2 ^p −1) (2 ^2p −1)... (2 ^ (2 ^k p) −1) in equation (2-1b). "bit string of p bit of" 00 ... 01, "and the least significant bit is" -1 a set of bit strings of p-bit ", it can be seen that a 2 ^k p point 2 was replicated to the ^{k + 1} p bit string of bits. Similarly to the case of β ₀ · (M / m ₀ ), the value obtained by multiplying the bit string of 2 ^{k + 1} p bits by 2 ^{p- (k + 1)} is 2 ^{k + 1} p By adding p- (k + 1) “0” s to the lower digits of the bit sequence of bits, the bit sequence is shifted to the upper digits by p- (k + 1) bits.

As in the case of β ₁ · (M / m ₁ ), the following equation (2-1c) is established in the case of β _i · (M / m _i ) (i <k + 1).

That is, (2 ^ (2 ^i-1 p) -1) is a 2 ⁱ p-bit bit string "00 ... 0011" in which the upper 2 ^i-1 p bits are "0" and the lower 2 ^i-1 p bits are "1". if ... 11 regarded as "value obtained by multiplying the ^{(2 ^ (2 i p)} +1) this value a bit string of the 2 ⁱ p bits, low-order 2 ⁱ p bits, and 2 ⁱ p bits higher 2 ⁱ p 2 were duplicated portions of bit ^{i + 1} p-bit bit string "00 ... 0011 ... 1100 ... 0011 ... 11" (0th bit (the 2 ^{i-1 p-1} bits from the least significant bit) digit side , And the 2 · 2 ^i-1 p bits to the 3 · 2 ^i-1 p-1 bits are “1” and the others are “0”).

The value obtained by multiplying (2 ^ (2 ^{i + 1} p) +1), ..., (2 ^ (2 ^k p) +1) in the same way as in the case of β ₁ · (M / m ₁ ) The 2 ⁱ p-bit bit string “00… 0011… 11” with the upper 2 ^i-1 p bits set to “0” and the lower 2 ^i-1 p bits set to “1” is copied to 2 ^{k-I + 1} locations. It can be seen that the bit string is 2 ^{k + 1} p bits. In other words, it is a bit string obtained by joining 2 ^ki bit strings of the 2 ⁱ p bits.

Then, the value obtained by multiplying the 2 ^{k + 1} p-bit bit string by 2 ^ (2 ^i-1 p- (k-i + 2)) in the same manner as in the case of β ₁ · (M / m ₁ ) Adds 2 ^i-1 p- (k-i + 2) “0” s to the lower digits of the 2 ^{k + 1} p-bit bit sequence to make the bit sequence 2 ^i-1 p- (k -i + 2) Bit string shifted to the upper digit side by bits.

If (2 ^ (2 ^i-1 p) -1) is regarded as a combination of 2 ^ (2 ^i-1 p) and -1, then (2 ^ (2 ^i-1 p) -1) Assume that the 2 ⁱ p bit string “00… 0100… 0 (-1)” is the second ^i-1 p bit is "1", the 0th bit is "-1", and the other bits are "0" Can do. Using this representation format, β _i · (M / m _i ) is 2 ⁱ⁻¹ p-bit bit string “00… 01” with the least significant bit “1” and 2 with the least significant bit “−1”. ^It can be seen that a bit string that is a duplicate of a bit string set of ^i-1 p bits is duplicated at 2 ^{k-I + 1} locations.

In the case of β _{k + 1} · (M / m _{k + 1} ), the following equation (2-1d) is established.

That is, (2 ^ (2 ^k p) -1) is a 2 ^{k + 1} p bit string “00… 0011… 11” in which the upper 2 ^k p bits are “0” and the lower 2 ^k p bits are “1”. Can be considered. The value obtained by multiplying the 2 ^{k + 1} p-bit bit string by 2 ^ (2 ^k p-1) is 2 ^k p-1 “0” in the lower digit of the 2 ^{k + 1} p-bit bit string. The bit string is shifted to the upper digit side by 2 ^k p-1 bits by adding "."

(1b) Property 2: Number of bits of multiplicand Each residue digit of the converted number Y = (y ₀ , y ₁ ,..., Y _{k + 1} ) expressed by a residue system with the equation (1-18) as a modulus set The remainder value y _i has the following properties.

・ When y ₀
Since y ₀ is a modulus (2 ^p −1) remainder value, it can be expressed by binary p bits.
・ Y _i (1 ≦ i ≦ k + 1)
Since y _i is a remainder value of modulus (2 ^ (2 ⁱ⁻¹ p) +1), it can be expressed by binary number 2 ⁱ⁻¹ p + 1 bits. However, the most significant bit is "1" only when y _i is the maximum value 2 ^ (2 ^i-1 p) = "100 ... 00 (2 ^i-1 p + 1 bits). In this case, all bits other than the most significant bit are “0”.

ここで、a_n,b_n,c_n,及びd_nは、２進表現の各桁である。 The following equation (2-2a) to (2-2d) shows a bit string of the remainder value y _i .

Here, a _n , b _n , c _n , and d _n are each digit of the binary representation.

(2) Acceleration of conversion to binary number for each remainder digit By the above property 1 and property 2, the multiplication part of the Chinese remainder theorem is realized by duplicating and concatenating the multiplicand y _i Can do. Thereby, in the conversion apparatus according to the present embodiment, an AND circuit (partial product) and a full adder necessary for normal multiplication can be eliminated.

A calculation example for y ₀ is shown in the following equation (2-3).

As shown in Property 2, y ₀ (= “a _p-1 a _p-2 ... A ₀ ”) is p bits. On the other hand, as shown in Expression (2-1a), β ₀ · (M / m ₀ ) is a bit string that becomes “1” for every p bits. Therefore, by copying y ₀ every p bits and adding “0” to the lower bits, the modulus corresponding conversion value y obtained by converting the remainder digit corresponding to the modulus m ₀ into a binary number without performing multiplication and addition. ₀ · β ₀ · (M / m ₀ ) can be obtained.

Next, a calculation example for y _i is shown in the following equation (2-4).

As shown in Property 2, y _i (= "c _{2 ^ (i-1) p} c _{2 ^ (i-1) p-1} ... c ₀ ") is 2 ^i-1 p + 1 bits. The maximum value is 2 ^ (2 ^i-1 p). Therefore, the maximum value of y _i multiplied by (2 ^ (2 ^ ^i-1 p) -1) (= "00..0100..0 (-1)") is 2 ^ (2 ⁱ p) -2 ^ (2 ^i-1 p), which can be expressed by a 2 ⁱ p-bit bit string (= "c _{2 ^ ip-1} 'c _{2 ^ ip-2} ' ... c ₀ '"). On the other hand, as shown in equations (2-1b) to (2-1d), β _i · (M / m _i ) becomes “00... 0100... 0 (-1)” every 2 ⁱ p bits. It is a bit string. Therefore, as in the case of _{y 0 y i · (2 ^} (2 ^ i-1 p) -1) (= "c 2 ^ ip-1 'c 2 ^ ip-2' ... c 0 '") if adding "0" to the lower bits by replicating bit string of the every 2 ⁱ p bits, based on the bit string, and converts the remainder digits corresponding to the modulus m _i without performing multiplications and additions to the binary number Modulus correspondence conversion values y _i · β _i · (M / m _i ) can be obtained.
The modulus-corresponding conversion value y _i · β _i · (M / m _i ) is shown in the following equation (2-5).

(3) EAC according to the equation (1-17) of (End-Around Carry) processing Chinese remainder theorem, after the product-sum operation of the multiplicand and the inverse, maximum value that can be represented by the residue system according modulus sets S _k It is necessary to calculate the remainder for the number M = 2 ^ (2 ^{k + 1} p) +1. This remainder calculation can be realized by the following EAC process.

When the modulus set shown in Formula (1-18) is used, since modulus M = 2 ^ (2 ^{k + 1} p) +1, 2 ^ (2 ^{k + 1} p) ≡1 (mod M) is To establish. Therefore, the following equation (2-6) is established from the addition / subtraction multiplication theorem of the residue system.

Here, 2 ^ (2 ^{k + 1} p) is a binary number of 2 ^{k + 1} p bits. Therefore, the formula (2-6), as shown in the following equation (2-7), the upper bit digit of from 2 ^{k + 1} p bits, by shifting the 2 ^{k + 1} p bit lower digit side , It shows that the remainder by modulus M can be calculated.

Using this, in EAC processing, a bit digit higher than 2 ^{k + 1} p bits in the value obtained by multiply-and-accumulate the remainder digit value and the reciprocal value is cyclically shifted to the least significant bit side and added. Then, the remainder value by the modulus M is calculated.

EAC processing for y _i · β _i · (M / m _i ) shown in equation (2-5) is shown in equation (2-8) below.

As shown in the equation (2-5), bits higher than 2 ^{k + 1} p bits in y _i · β _i · (M / m _i ) are 2 ^i-1 p- (k-i + 2) Is a bit. On the other hand, since y _i · β _i · (M / m _i ) has the lower 2 ^i-1 p- (k-i + 2) bits "0", y _i · β _i · (M / m _i ), The remainder value by M of y _i · β _i · (M / m _i ) can be obtained only by moving the higher-order bit digits than 2 ^{k + 1} p bits to the lower bits.

(4) Speed up of addition between remainder digits Addition of conversion values y _i · β _i · (M / m _i ) corresponding to the modulus in equation (1-29) is reduced and speeded up by the following method Can be achieved. Here, for simplicity, a modulus set in which p = 3 and k = 2 in Equation (1-18) is shown as an example. That is, the modulus set S _k = {m ₀ , m ₁ , m ₂ , m ₃ } = {7 (= 2 ³ -1), 9 (= 2 ³ +1), 65 (= 2 ⁶ +1), 4097 (= 2 ¹² +1)}. The number M of numerical values that can be expressed in this residue system is (2 ²⁴ -1). If a certain numerical value expressed in the remainder system is (y ₀ , y ₁ , y ₂ , y ₃ ), each binary expression is expressed by the following equations (2-9a) to (2-9d).

  Using the properties of the Chinese remainder theorem shown in (1) above, the properties of the residue digit shown in (2), and the EAC processing shown in (3), the calculation method shown in FIG. It is possible to calculate the person's remainder theorem.

First, corresponding to the modulus m ₀ , the partial bit string y ₀ (= “a ₂ a ₁ a ₀ ”) of 3 (= p) bits is copied as a 3-bit bit string of the upper digits, and the same partial bit string is A 6-bit addend number “a ₂ a ₁ a ₀ a ₂ a ₁ a ₀ ” including a bit string and a lower bit string is generated. This added number is a bit string corresponding to the product of 2p bits “00... 0100... 01” and y ₀ in equation (2-1a), and “a _p-1 a _p in equation (2-3)”. _-2 ... a ₀ a _p-1 a _p-2 ... a ₀ "

Next, from the value obtained by shifting the remainder value y ₁ of 4 (= 2 ^(1-1) p + 1) bits to the upper digit side of 3 (= 2 ^(1-1) p bits, corresponding to the modulus m ₁ A 6 (= 2 ¹ p) -bit partial bit string “b ₅ ′ b ₄ ′ b ₃ ′ b ₂ ′ b ₁ ′ b ₀ ′” obtained by subtracting the remainder value y ₁ is generated.

Next, the 6-bit addend "a ₂ a ₁ a ₀ a ₂ a ₁ a ₀ " and the partial bit string "b ₅ 'b ₄ ' b ₃ 'b ₂ ' b ₁ 'b ₀ '" Addition is performed by a 6-bit adder, and EAC processing is performed to obtain a 6-bit bit string “s ₅ s ₄ s ₃ s ₂ s ₁ s ₀ ”. In this EAC process, the carry of the most significant bit is added to the least significant bit as a result of the original 24-bit addition. However, because of the regularity of the added number and the modulus-corresponding conversion value, the carry bit of the most significant bit is the same as the carry bit obtained from the addition of the lower 6 bits, so a carry bit by 6-bit addition can be used.

Here, the modulus-corresponding conversion values corresponding to the moduli m ₀ and m ₁ are the above-mentioned values as shown in the equations (2-1a), (2-1b), (2-4) and (2-5). This is a bit string obtained by combining the addition number and four partial bit strings. Therefore, the sum of the modulus-corresponding conversion values corresponding to the moduli m ₀ and m ₁ is a bit string obtained by combining four 6-bit bit strings “s ₅ s ₄ s ₃ s ₂ s ₁ s ₀ ”. Therefore, in order to add a modulus-corresponding conversion value corresponding to the modulus m ₂ to this sum, the 6-bit bit string “s ₅ s ₄ s ₃ s ₂ s ₁ s ₀ ” is copied as a 6-bit bit string of upper digits, A 12-bit addend number “s ₅ s ₄ s ₃ s ₂ s ₁ s ₀ s ₅ s ₄ s ₃ s ₂ s ₁ s ₀ ” including the bit string as an upper bit string and a lower bit string is generated.

Next, corresponding to the modulus m ₂ , a value obtained by shifting the remainder value y ₂ of 7 (= 2 ^(2-1) p + 1) bits to the upper digit side of 6 (= 2 ^(2-1) p) bits Bit sequence "c ₁₁ 'c ₁₀ ' c ₉ 'c with the remainder y ₂ subtracted from" 0 0 0 0 "(= 2 ^2-1 p- (k-i + 2)) bits added to the lower digit _{8 'c 7' c 6 '} c 5' c 4 'c 3' c 2 'c 1' c 0 ' to generate a 0 0 0 0 ". Then, the EAC processing shown in Expression (2-8) is performed, and the 12 (= 2 ² p) bit partial bit string “c ₇ ′ c ₆ ′ c ₅ ′ c ₄ ′ c ₃ ′ c ₂ ′ c ₁ ′ c generating a _{0 'c 11' c 10 '} c 9' c 8 '".

Next, the 12-bit addend "s ₅ s ₄ s ₃ s ₂ s ₁ s ₀ s ₅ s ₄ s ₃ s ₂ s ₁ s ₀ " and the partial bit string "c ₇ 'c ₆ ' c ₅ ' c ₄ 'c ₃ ' c ₂ 'c ₁ ' c ₀ 'c ₁₁ ' c ₁₀ 'c ₉ ' c ₈ '"is added by a 12-bit adder, and EAC processing is performed in the same way as addition to the modulus m ₀ and m ₁ To obtain a 12-bit bit string “t ₁₁ t ₁₀ t ₉ t ₈ t ₇ t ₆ t ₅ t ₄ t ₃ t ₂ t ₁ t ₀ ”.

Similarly, the 12-bit bit string is copied to the upper 12 bits, and a 24-bit addend number including the 12-bit bit string as the upper and lower bit strings is generated. Then, by adding a modulus-corresponding conversion value corresponding to the modulus m ₃ to the added number and performing EAC processing, a converted value obtained by converting the converted number into a binary number can be obtained.

  In the conversion device according to the present embodiment, as described above, the Chinese remainder theorem can be calculated at a high speed with a smaller amount of hardware by utilizing the fact that the binary representation of the reciprocal number has regularity. .

FIG. 2 shows a configuration of the conversion apparatus 10 according to the present embodiment. The conversion device 10 converts a converted number expressed by a residue system into a binary number. The coset is a set of a plurality of remainder value y _i obtained by dividing the target conversion number Y by each of the plurality of modulus m _i, is intended to represent the transformation number Y. As an example, conversion device 10 according to this embodiment, as a set of the plurality of modulus m _i, using the modulus sets S _k shown in equation (1-18).

The minimum modulus m ₀ in the modulus set S _k shown in the equation (1-18) is a natural number of 2 or more obtained by subtracting 1 from the power value of the natural number p of 2. Each of the non-minimum moduli m ₁ ,..., M _{k + 1} among the plurality of moduli takes a value obtained by adding 1 to a power value obtained by raising 2 to a power of a natural number. Here, the power value takes a value larger than the product of the modulus smaller than the modulus, and may be the smallest power value 2 ^ (2 ^i-1 p) larger than the product of the modulus smaller than the modulus.

The conversion apparatus 10 according to the present embodiment converts a binary modulus-corresponding conversion value y _i · β _i · (M / m _i ), which is the product of the remainder value and the reciprocal in the Chinese remainder theorem, by duplicating the bit string. Realize. As a result, the conversion apparatus 10 can convert the converted number Y into a binary number at a high speed with a small amount of hardware.

The conversion apparatus 10 includes a modulus-corresponding conversion value generation unit 100 and a modulus-corresponding conversion value adding unit 130.
The modulus-corresponding conversion value generation unit 100 calculates, for each of the plurality of moduli m ₀ ,..., M _{k + 1} , the modulus remainder value y _i (= “α _{2 ^ (i−1) p} α _{2 ^ (i−1) ) p-1 ... α 0 "} ) to the basis of the modulus m _i other than the modulus of the product (M / m _i) the value y _i · multiplied (M / m _i), 2 binary number corresponding to the modulus A modulus-corresponding conversion value y _i · β _i · (M / m _i ) as a value is generated.

The modulus conversion value generation unit 100 includes one or more partial bit string generation units 110 (110a to d) and one or more partial bit string replication units 120 (120a to d). Each of the partial bit string generation units 110a to 110d is converted to a modulus-corresponding conversion value corresponding to the modulus m _i on the basis of the remainder value y _i obtained by dividing the conversion target Y by the modulus m _i corresponding to the partial bit string generation unit 110. Generate a partial bit string (= "α _{2 ^ ip-1} 'α _{2 ^ ip-2} '… α ₀ ') that is a part of y _i · β _i · (M / m _i ), where the smallest The partial bit string generation unit 110a corresponding to the modulus m ₀ outputs the value y ₀ (= “a _p-1 a _p-2 ... A ₀ ”) as the partial bit string, while corresponding to the non-minimum modulus m _i . partial bit string generating unit 110b~d to as partial bit string, the remainder value y _i of the ^{(2 ^ (2 ^ i-} 1 p) -1) (= "00..0100..0 (-1)") The multiplied value is output.

Each of the partial bit string duplication units 120a to 120d is a partial bit string generated by the partial bit string generation unit 110 at a plurality of locations of the modulus-corresponding conversion values y _i · β _i · (M / m _i ) corresponding to the partial bit string duplication unit 120. Duplicate. This partial bit string duplication unit 120 by generates modulus corresponding conversion value y _i · β _i · multiplied by the modulus m _i the partial bit string (M / m _i). Here, the partial bit string duplication unit 120d corresponding to the maximum modulus m _{k + 1} uses the bit string generated by the partial bit string generation unit 110 as the modulus corresponding conversion value y _{k + 1} · β _{k + 1} · (M / m _{k +1} ).

The modulus-corresponding conversion value adding unit 130 adds the modulus-corresponding conversion values for each of the plurality of moduli m ₀ ,... M _{k + 1} to calculate a binary converted number bin Y. Each partial bit string generation unit 110 and each partial bit string duplication unit 120 described above are preferably realized by separate circuits for each modulus, but instead, the same circuit is used for each modulus in turn. A configuration for processing can also be adopted.
Note that each set of remainder value y _i of the transformation number Y may be entered in a different arrangement and order of the modulus sets S _k. In this case, converter 10 may further comprise a sequence modulus set S remainder value sorting unit to sort the order of _k multiple remainder value y _i.

FIG. 3 shows a configuration of the partial bit string generation unit 110 according to the present embodiment. Partial bit string generation unit 110 shown in FIG. 3, the modulus m ₁ not the smallest, ... m _{k + 1} provided corresponding to the remainder value y _i of the modulus _{m i (= "α 2 ^} (i _-1) Generate partial bit sequence (= "α _{2 ^ ip-1} 'α _{2 ^ ip-2} '… α ₀ '") from _p α _{2 ^ (i-1) p-1} … α ₀ ") . This partial bit string corresponds to the bit string "c _{2 ^ ip-1} 'c _{2 ^ ip-2} '... C ₀ '" in Expression (2-4).

Partial bit string generation unit 110 includes a complement calculator 200 and an adder 210. Complement calculator 200, the modulus m _i corresponding to the 2 ^i-1 p + ^1-bit remainder value _{y i (= "α 2 ^} (i-1) p α 2 ^ (i-1) p-1 ... α ₀ ") is input, and the complement of the remainder value y _i is calculated. The complement computing unit 200 according to the present embodiment outputs a 2 ⁱ p-bit bit string that is a 2's complement of the remainder value y _i .

The adder 210 performs a complement operation unit 200 on the lower 2 ^i-1 p bits of the remainder value y _i (= "α _{2 ^ (i-1) p} α _{2 ^ (i-1) p-1} ... α ₀ "). Adds the upper 2 ^i-1 p bits of the complement output by. Then, the adder 210 adds the addition result to the upper digits of the lower 2 ^i-1 p bits of the complement, and generates a partial bit string of 2 ⁱ p bits (= "α _{2 ^ ip-1} α _{2 ^ ip-2} ... α ₀ ") is generated. As a result, the adder 210 converts the remainder value y _i (= “α _{2 ^ (i−1) p} α _{2 ^ (i−1) p−1} ... Α ₀ ”) to the natural number corresponding to the modulus m _i. A partial bit string having a value obtained by subtracting the remainder value from the value shifted to the upper digit side by the number of bits 2 ^i-1 p can be generated.

FIG. 4 shows a configuration of the partial bit string duplication unit 120 according to the present embodiment. The partial bit string duplication unit 120 includes a duplicator 300 and an EAC calculator 310. As shown in the equation (2-3), the duplicator 300 corresponding to the minimum modulus m ₀ has a plurality of locations corresponding to the modulus m ₀ corresponding to the modulus m ₀ , more specifically 2 ^{k + 1} locations. Secondly, the partial bit string is duplicated at p bit intervals. The duplicator 300 corresponding to the modulus m _i that is not the minimum and the maximum is, as shown in Expression (2-4), a plurality of places corresponding to the modulus corresponding to the modulus m _i , more specifically, 2 ^{k−. The} partial bit string is duplicated at 2 ⁱ · p bit intervals at ^{i + 1} locations. As a result, the replicator 300 combines 2 ^{k−i + 1} partial bit strings. The bit string obtained in this way becomes a modulus-corresponding conversion value y _i · β _i · (M / m _i ) if 2 ^i-1 p- (k-i + 2) bits are added to the lower bits. Takes a value. Largest duplicator 300 corresponding to the modulus m _{k + 1,} as can be seen from equation (2-1d), the one place of the modulus corresponding conversion value corresponding to the modulus m _i, replicating the partial bit string.

As shown in the equation (2-8), the EAC computing unit 310 sets the upper 2 ^i-1 p- (k−i + 2) bits of the bit string output from the duplicator 300 to the lower bit side of the bit string. EAC processing is performed by cyclic shift. As a result, the EAC computing unit 310 can obtain the modulus-corresponding conversion value y _i · β _i · (M / m _i ) that has been subjected to EAC processing.

According to the partial bit string duplicating unit 120 shown above, the partial bit string is duplicated at a plurality of locations, and the upper bit is moved to the lower bit, whereby the modulus corresponding conversion value y _i · β _i · (M / m _i ) is obtained. Obtainable. Therefore, the partial bit string duplication unit 120 does not use an arithmetic circuit such as a multiplier or an adder, and the modulus-corresponding conversion values y _i , β _i , (M / m _i) can be obtained by duplicating the partial bit string and moving some bits. ) Can be generated, and processing can be performed at high speed with a small amount of hardware.

FIG. 5 shows an operation flow of the conversion apparatus 10 according to the present embodiment.
First, each of the plurality of partial bit string generation units 110 generates a partial bit string corresponding to the remainder digit based on the remainder value y _i for the corresponding remainder digit (S400).

Next, each of the plurality of partial bit string duplication units 120 duplicates the partial bit string for the corresponding remainder digit and performs EAC processing (S410). Partial bit string duplication unit 120 by this process, the remainder value y _i by the modulus m _i of the transformation number Y, the remainder value remainder value corresponding to the modulus m _i corresponds to one and the other modulus becomes 0 By multiplying a binary value, that is, a value such as b) in the formula (1-14), a modulus-corresponding conversion value y _i · β _i · (M / m _i ) for the remainder digit can be generated.

  Then, the modulus-corresponding conversion value adding unit 130 calculates the sum by adding all the modulus-corresponding conversion values, and outputs the sum as a binary representation of the converted number Y.

  According to the conversion device 10 described above, the residue-based converted number Y can be converted to a binary number at high speed with a small amount of hardware.

Instead of the above, the conversion apparatus 10 may obtain a modulus-corresponding conversion value by using a bit string replica for only some of the moduli. That is, 2 raised to the power by a natural number, the product is greater than a power value smaller modulus than the modulus, if the modulus m _i is present with taking a value obtained by adding 1, for the modulus m _i is less than the modulus m _j above The process of S410 may be performed.

  FIG. 6 shows a configuration of the conversion apparatus 10 according to a modification of the present embodiment. The conversion apparatus 10 according to the present modification converts the number to be converted expressed by a residue system into a binary number. This residue system is the same as the residue system described with reference to FIG.

  When the conversion apparatus 10 according to the present modification adds the partial bit strings corresponding to the respective moduli, the conversion apparatus 10 uses the added number obtained by copying the lower bit string of the partial sum to the upper bit string. Thereby, the conversion apparatus 10 can reduce the number of bits of the adder in accordance with the number of bits of the remainder value corresponding to each modulus, and can reduce the number of conversions Y of the residue system to 2 at high speed with a small amount of hardware. Can be converted to hexadecimal.

The conversion apparatus 10 includes one or a plurality of partial bit string generation units 110 (110a to 110d) and a modulus corresponding conversion value addition unit 600. Each of the partial bit string generation unit 110, a plurality of moduli m _0, ..., for each m _{k + 1,} at least the modulus corresponding conversion value y _i · β _i · corresponding to the modulus m _i (M / m _i) A partial bit string (= "α _{2 ^ ip-1} α _{2 ^ ip-2} ... α ₀ ") included in a part is generated. This modulus-corresponding conversion value is a binary value based on a value obtained by multiplying a modulus other than the modulus among a plurality of moduli, as in the conversion device 10 of FIG. Here, the partial bit string generation unit 110 according to this modification has the same function and configuration as the partial bit string generation unit 110 illustrated in FIGS.

Modulus corresponding conversion value adding unit 600, a plurality of moduli m _0, ..., based on partial bit strings for each of the m _{k + 1,} a plurality of moduli m _0, ..., modulus corresponding conversion for each of the m _{k + 1} A binary converted number is calculated by adding the values y _i , β _i, and (M / m _i ). The modulus-corresponding conversion value addition unit 600 includes one or more lower-order bit string duplication units 610 (610a, 610b, 610c,...) And one or more bit string addition units 620 (620a, 620b,..., 620d).

Each lower bit string copying unit 610, a plurality of moduli m _0, ..., modulus m ₁ is not the smallest among the m _{k + 1,} ..., is provided corresponding to each of the m _{k + 1.} As shown in FIG. 1, the lower-order bit string duplication unit 610 converts the modulus-corresponding conversion values y ₀ · β ₀ · (M / m ₀ ),..., Y _i− corresponding to all moduli smaller than the corresponding modulus m _i. A lower bit string having a predetermined number of bits included in a part of the first partial sum which is the sum of ₁ · β _i-1 · (M / m _i-1 ) Duplicate as. As a result, the lower bit string duplication unit 610 generates an addend number including the same upper bit string and lower bit string. In this case, lower bit string copying unit 610a provided corresponding to the modulus m ₁ is the low-order bit string of the first partial sum, using the bit sequence of the remainder value y ₀ of the partial bit string generating unit 110a is output.

Each bit string adding unit 620, a plurality of moduli m _0, ..., modulus m ₁ is not the smallest among the m _{k + 1,} ..., is provided corresponding to each of the m _{k + 1.} Bit string adding section 620, as shown in FIG. 1, the augend generated by lower bit string duplication unit 610 for the corresponding modulus m _i, is produced by the partial bit string generation unit 110 in correspondence with the modulus m _i Add the partial bit strings. Thus the bit string adding section 620, the modulus m _i is less than all of the moduli m _0, ..., the first partial sum calculated for m _i-1, was added a modulus corresponding conversion values for the modulus m _i A lower-order bit string included in at least a part of the second partial sum is calculated. The lower bit string, modulus m _0, ..., as lower bit string of the partial sum calculated for m _i, is input to the lower bit string copying unit 610 that corresponds to the modulus m _{i + 1} large following the modulus m _i. Then, the bit string calculated by the bit string adding unit 620d corresponding to the maximum modulus m _{k + 1} is the sum of all the modulus-corresponding conversion values, and is output as a binary expression bin Y of the converted number.

FIG. 7 shows a configuration of the lower-order bit string duplication unit 610 according to a modification of the present embodiment. Lower bit string copying unit 610, the corresponding modulus m _i modulus corresponding conversion value corresponding to all the modulus less than _{y 0 · β 0 · (M} / m 0), ..., y i-1 · β i-1 · ( The lower bit string of the first partial sum which is the sum of M / m _i-1 ) is input. Then, the lower bit string of the p · 2 ^i-1 bits, and replicated as p · 2 ^i-1 bits of the upper bit string of the upper digit from the lower bit string, and generates a augend of p · 2 ⁱ bits.

According to lower bit string copying unit 610 shown above, the number of the addition of the partial bit strings and the same number of bits corresponding to the modulus m _i may be produced by replication of the bit string.

FIG. 8 shows a configuration of a bit string adder 620 according to a modification of the present embodiment. The bit string adder 620 includes an adder 800 and an EAC calculator 810. The adder 800, as shown in FIG. 1, the augend for the corresponding modulus m _i, adds the partial bit string of the lower p · 2 ⁱ bits in the modulus corresponding conversion value corresponding to the modulus m _i. The EAC computing unit 810, in the case where an overflow exceeding the number of the added number and the number of bits of the partial bit string occurs due to the addition, in the bit string obtained as a result of the addition, as shown in Expression (2-8) and FIG. The EAC process is performed by adding the overflowing bits to the lower bits of the lower bit string having the same number of bits as the added number.

According to the bit string adding unit 620 shown above, p in the second partial sum plus modulus corresponding conversion value _{y i · β i · (M} / m i) of the modulus m _i in the first partial sum・ 2 ^i- bit lower bit string can be calculated.

FIG. 9 shows an operation flow of the conversion apparatus 10 according to the modification of the present embodiment.
First, each of the plurality of partial bit string generation units 110 generates a partial bit string corresponding to the remainder digit based on the remainder value y _i for the corresponding remainder digit (S400). Next, the modulus-corresponding conversion value adding unit 600 repeats the processing from S910 to S930 corresponding to each of the non-minimum moduli m ₁ ,..., M _{k + 1} (S900, S940).

In the iterative process, the lower bit string duplication unit 610 corresponding to the modulus m _i to be processed duplicates the lower bit string of the (i−1) th partial sum to the upper bit string to generate the i th added number (S910). . Next, the bit string addition unit 620 corresponding to the modulus m _i to be processed adds the i-th partial bit string to the i-th added number (S920). Then, the bit string adder 620 performs EAC processing on the addition result, and generates a lower bit string of the i-th partial sum (S930).

  By repeating the above processing (S940), the sum of all the modulus-corresponding conversion values can be output from the bit string adder 620 at the final stage.

As an example, p = 3, k = 2, and the modulus set is S _k = {m ₀ , m ₁ , m ₂ , m ₃ } = (7 (= 2 ³ -1), 9 (= 2 ³ +1) , 65 (= 2 ⁶ +1), 4097 (= 2 ¹² +1)}, the number of transforms (y ₀ , y ₁ , y ₂ , y ₃ ) = (5 , 6, 47, 3125) show the calculation to convert the binary representation by applying the Chinese remainder theorem. The binary representation of each remainder value is y ₀ = “101”, y ₁ = “110”, y ₂ = “101111”, y ₃ = “110000110101”.

First, the complement computing unit 200 sets the two's complement (−y ₁ ) = “111010”, (−y ₂ ) = “111111010001”, (−y ₃ ) = “111111111111001111001011” for y ₁ , y ₂ , y _3. Is calculated. Then, the adder 210, - by adding y ₁ to the MSB side of (y _1), obtain a partial bit string "101010". Similarly, the adder 210 adds y ₂ and y ₃ to the MSB side of (−y ₂ ) and the MSB side of (−y ₃ ) to obtain partial bit strings “101110010001” and “110000110100001111001011”. The adder 210 performs EAC processing of 4 bits for y ₂ · β ₂ · (M / m ₂ ) and 11 bits for y ₃ · β ₃ · (M / m ₃ ) based on the property 1 described above. Do. As a result, the adder 210 obtains the partial bit strings “100100011011” and “000111100101111000011010” that have been subjected to EAC processing. This corresponds to the partial product of the multiplication part in the Chinese remainder theorem.

Next, the lower-order bit string duplication unit 610a duplicates y ₀ = “101” in two places to obtain the added number “101101”. The bit string adder 620a performs EAC processing on the MSB of the bit string “1010111” obtained by adding the added number and the partial bit string “101010” to obtain the lower bit string “011000” of the partial sum (partial sum 1) corresponding to the modulus m ₁ Yeah.

Next, the lower-order bit string duplicating unit 610b duplicates this partial sum 1 in two places to obtain the added number “011000011000”. The bit string adding unit 620b obtains a bit string “111100110011” obtained by adding the added number and the partial bit string “100100011011”. Since the carry in bit 13 does not occur, EAC processing is not required, the lower bit string of the partial sums this bit string corresponds to the modulus m ₂ (partial sum 2).

  Next, the lower-order bit string duplicating unit 610c duplicates this partial sum 2 in two places to obtain the added number “111100110011111100110011”. The bit string adder 620c performs EAC processing on the MSB of the bit string “1000100011001110101001101” obtained by adding the added number and the partial bit string “000111100101111000011010” to obtain a 24-bit numerical value “000100011001110101001110” obtained by converting the converted number into a binary number. When this number is expressed in decimal, it becomes 1154382, and this number is the calculation result of the Chinese remainder theorem for (y0, y1, y2, y3) = (5, 6, 47, 3125).

According to the conversion device 10 shown above, the modulus corresponding conversion value adding unit 600, corresponding to the modulus m _i for adding the augend and partial bit strings, the number of bits augend and partial bit string An adder 800 with a corresponding number of bits can be used. That is, the bit string adding unit 620, the first modulus m ^_i1, p · 2 _i1 to augend bits, the addition of p · 2 ⁱ¹ bits for adding the partial bit string of p · 2 ⁱ¹ bits in modulus corresponding conversion value a vessel 210, the second modulus m _i2, the augend of p · 2 ⁱ² bits, the p · 2 ⁱ² bits for adding the partial bit string of p · 2 ⁱ² bits in modulus corresponding conversion value and an adder 210 It can be prepared separately. As a result, an adder having a small number of bits can be used for a modulus having a small value, and conversion of the number to be converted can be performed more quickly with a small amount of hardware.

Instead of the above, the conversion apparatus 10 may obtain the addend number by using bit string duplication only for some moduli. That is, for the first modulus m _i in the lower bit string copying unit 610, included as part of the first partial sum is the sum of the modulus corresponding conversion value corresponding to a first modulus m _i is smaller than at least one modulus The lower bit string may be copied as the upper bit string, and the added number including the same upper bit string and the lower bit string may be generated. In this case, the bit string adding unit 620, to the augend, by adding the partial bit string corresponding to the first modulus m _i, to generate a bit string included in at least part of the second partial sum.

  FIG. 10 shows an example of a hardware configuration of a computer 1900 according to this embodiment. A computer 1900 according to this embodiment is connected to a CPU peripheral unit having a CPU 2000, a RAM 2020, a graphic controller 2075, and a display device 2080 that are connected to each other by a host controller 2082, and to the host controller 2082 by an input / output controller 2084. Input / output unit having communication interface 2030, hard disk drive 2040, and CD-ROM drive 2060, and legacy input / output unit having ROM 2010, flexible disk drive 2050, and input / output chip 2070 connected to input / output controller 2084 With.

  The host controller 2082 connects the RAM 2020 to the CPU 2000 and the graphic controller 2075 that access the RAM 2020 at a high transfer rate. The CPU 2000 operates based on programs stored in the ROM 2010 and the RAM 2020 and controls each unit. The graphic controller 2075 acquires image data generated by the CPU 2000 or the like on a frame buffer provided in the RAM 2020 and displays it on the display device 2080. Instead of this, the graphic controller 2075 may include a frame buffer for storing image data generated by the CPU 2000 or the like.

  The input / output controller 2084 connects the host controller 2082 to the communication interface 2030, the hard disk drive 2040, and the CD-ROM drive 2060, which are relatively high-speed input / output devices. The communication interface 2030 communicates with other devices via a network. The hard disk drive 2040 stores programs and data used by the CPU 2000 in the computer 1900. The CD-ROM drive 2060 reads a program or data from the CD-ROM 2095 and provides it to the hard disk drive 2040 via the RAM 2020.

  The input / output controller 2084 is connected to the ROM 2010, the flexible disk drive 2050, and the relatively low-speed input / output device of the input / output chip 2070. The ROM 2010 stores a boot program that the computer 1900 executes at startup, a program that depends on the hardware of the computer 1900, and the like. The flexible disk drive 2050 reads a program or data from the flexible disk 2090 and provides it to the hard disk drive 2040 via the RAM 2020. The input / output chip 2070 connects various input / output devices via a flexible disk drive 2050 and, for example, a parallel port, a serial port, a keyboard port, a mouse port, and the like.

  A program provided to the hard disk drive 2040 via the RAM 2020 is stored in a recording medium such as the flexible disk 2090, the CD-ROM 2095, or an IC card and provided by the user. The program is read from the recording medium, installed in the hard disk drive 2040 in the computer 1900 via the RAM 2020, and executed by the CPU 2000.

  A program that is installed in the computer 1900 and causes the computer 1900 to function as the conversion device 10 shown in FIG. 2 includes a modulus-corresponding conversion value generation module having a partial bit string generation module and a partial bit string duplication module, and a modulus-corresponding conversion value addition module. Prepare. These programs or modules work with the CPU 2000 or the like to convert the computer 1900 into a modulus-corresponding conversion value generation unit 100 having one or a plurality of partial bit string generation units 110 and one or a plurality of partial bit string duplication units 120, and a modulus corresponding conversion. Each of them functions as the value adder 130. The partial bit string generation module includes a complement calculation program and an addition program. These programs work on the CPU 2000 or the like to cause the computer 1900 to function as the complement calculator 200 and the adder 210, respectively. The partial bit string duplication module includes a duplication program and an EAC operation program. These programs work on the CPU 2000 or the like to cause the computer 1900 to function as the duplicator 300 and the EAC calculator 310, respectively.

  A program that is installed in the computer 1900 and causes the computer 1900 to function as the conversion device 10 illustrated in FIG. 6 includes a partial bit string generation module, a low-order bit string duplication module, and a modulus-compatible conversion value generation module including a bit string addition module, a modulus And a corresponding conversion value addition module. These programs or modules operate on the CPU 2000 or the like to convert the computer 1900 into one or more partial bit string generation units 110, one or a plurality of lower bit string duplication units 610, and a bit string addition unit 620. Each of them functions as 600. The bit string addition module includes an addition program and an EAC operation program. These programs or modules work on the CPU 2000 or the like to cause the computer 1900 to function as the adder 800 and the EAC calculator 810, respectively.

  The program or module shown above may be stored in an external storage medium. As the storage medium, in addition to the flexible disk 2090 and the CD-ROM 2095, an optical recording medium such as DVD or CD, a magneto-optical recording medium such as MO, a tape medium, a semiconductor memory such as an IC card, or the like can be used. Further, a storage device such as a hard disk or a RAM provided in a server system connected to a dedicated communication network or the Internet may be used as a recording medium, and the program may be provided to the computer 1900 via the network.

  FIG. 11 shows the result of comparing the circuit scale and calculation time of the conversion apparatus 10 shown in FIG. 6 with the calculation method in the prior art (Non-Patent Document 2). Here, the number of transistors of the 1-bit half adder (about 15 transistors) is 1HA, and the delay of the 1-bit half adder is 1D. In this case, the circuit scale and delay of the 1-bit full adder are 2HA and 2D, respectively. Since the complement calculation is performed in common in the prior art and the conversion apparatus 10, it is omitted.

The modulus set is S _k = {m ₀ , m ₁ , m ₂ , m ₃ } = {7 (= 2 ³ -1), 9 (= 2 ³ +1), 65 (= 2 ⁶ +1), 4097 ( = 2 ¹² +1)}, the prior art requires 3 stages of 24-bit full adders and 3 stages of half adders (12 bits) for EAC processing, and the circuit scale is 24 × 2HA × 3 + 12HA × 3 = 180HA. In Non-Patent Document 2, the delay amount is (3 stages of delay of a 24-bit adder) + (EAC delay) = 24 × 2D × 3 + 12 × 1D = 156D.

  On the other hand, according to the converter 10, the circuit scale is (6 bit full adder) + (12 bit full adder) + (24 bit full adder) + (3 bit EAC) + (6 bit EAC) + (12-bit EAC) + (3-bit EAC) + (6-bit EAC) + (12-bit EAC) = 6 × 2HA + 12 × 2HA + 24 × 2HA + 3HA + 6HA + 12HA + 3HA + 6HA + 12HA = 126HA Become. Also, the delay is (6 bit adder delay) + (12 bit adder delay) + (24 bit adder delay) + (12 bit EAC delay) + (12 bit EAC delay) = 6 x 2D + 12 × 2D + 24 × 2D + 12 × 1D + 12 × 1D = 108D.

Therefore, when the above-described modulus set is used, the conversion device 10 can reduce the circuit scale by 30% and the delay by 30% compared to the related art. In addition, when arbitrary p and k are taken into consideration, in the conventional technique, the circuit scale and the delay increase in proportion to k. On the other hand, in the conversion device 10, the circuit scale and the delay are proportional to (2 + 2 ^−k ). Therefore, the conversion device 10 can reduce the circuit scale and the delay as the k increases, as compared with the conventional technique.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above-described embodiment. It is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.

An example of the calculation method of the Chinese remainder theorem concerning embodiment of this invention is shown. 1 shows a configuration of a conversion apparatus 10 according to an embodiment of the present invention. 2 shows a configuration of a partial bit string generation unit 110 according to an embodiment of the present invention. 2 shows a configuration of a partial bit string duplication unit 120 according to an embodiment of the present invention. The operation | movement flow of the converter 10 which concerns on embodiment of this invention is shown. The structure of the converter 10 which concerns on the modification of embodiment of this invention is shown. The structure of the low-order bit stream duplication part 610 which concerns on the modification of embodiment of this invention is shown. The structure of the bit string addition part 620 which concerns on the modification of embodiment of this invention is shown. The operation | movement flow of the converter 10 which concerns on the modification of embodiment of this invention is shown. 2 shows an exemplary hardware configuration of a computer 1900 according to an embodiment of the present invention. The comparison result with the converter 10 concerning embodiment of this invention and a prior art is shown.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Conversion apparatus 100 Modulus corresponding | compatible conversion value production | generation part 110a-d Partial bit string production | generation part 120a-d Partial bit string duplication part 130 Modulus correspondence conversion value addition part 200 Complement arithmetic unit 210 Adder 300 Duplicator 310 EAC arithmetic unit 600 Modulus correspondence conversion value Adder 610a-d Lower bit string duplicator 620a-d Bit string adder 800 Adder 810 EAC calculator 1900 Computer 2000 CPU
2010 ROM
2020 RAM
2030 Communication interface 2040 Hard disk drive 2050 Flexible disk drive 2060 CD-ROM drive 2070 Input / output chip 2075 Graphic controller 2080 Display device 2082 Host controller 2084 Input / output controller 2090 Flexible disk 2095 CD-ROM

Claims (9)

A conversion device that converts a converted number expressed by a residue system into a binary number,
The residue system represents the converted number by a set of a plurality of remainder values obtained by dividing the converted number by each of a plurality of moduli,
The first modulus is a value obtained by adding 1 to a power value larger than the product of the modulus less than the first modulus, which is a power of 2 by a natural number,
For each of a plurality of moduli, at least a part of a conversion value corresponding to a modulus corresponding to the modulus, which is a binary value based on a value obtained by multiplying the remainder of the modulus by a product of a modulus other than the modulus. A partial bit string generation unit for generating the included partial bit string;
A modulus-corresponding conversion value adding unit that calculates the binary converted number by adding the modulus-corresponding conversion value for each of the plurality of moduli based on the partial bit string for each of the plurality of moduli. ,
The modulus corresponding conversion value adding unit is
A lower-order bit string having a predetermined number of bits included in a part of the first partial sum that is the sum of the modulus-corresponding conversion values corresponding to at least one of the moduli smaller than the first modulus is a higher-order digit than the lower-order bit string. A lower bit string duplicating unit that replicates as an upper bit string of the same and generates an added number including the same upper bit string and lower bit string;
At least a part of the second partial sum obtained by adding the partial bit string corresponding to the first modulus to the added number and adding the modulus corresponding conversion value for the first modulus to the first partial sum. A conversion apparatus comprising: a bit string addition unit that calculates a lower bit string included therein. The minimum modulus is a natural number of 2 or more obtained by subtracting 1 from a power value of 2 natural numbers;
Each of the non-minimum moduli of the plurality of moduli takes a value obtained by adding 1 to a power value larger than the product of the moduli smaller than the modulus obtained by raising 2 by a natural number,
The lower-order bit string duplicating unit, for each of the non-minimum moduli of the plurality of moduli, includes a part of the first partial sum that is a sum of the modulus-corresponding conversion values corresponding to all the moduli smaller than the moduli. A lower bit string of a predetermined number of bits included is copied as an upper bit string of higher digits than the lower bit string, and the added number for the modulus is generated,
For each of the non-minimum moduli of the plurality of moduli, the bit string adding unit adds the partial bit string corresponding to the modulus to the added number for the modulus, and adds the partial bit string corresponding to the first partial sum. The conversion apparatus according to claim 1, wherein a lower-order bit string included in at least a part of the second partial sum obtained by adding the modulus-corresponding conversion value for a modulus is calculated. The plurality of moduli takes the values shown in the following Equation 1,
The low-order bit string duplicating unit, for each of the non-minimum moduli m _i (i = 1,..., K + 1) among the plurality of moduli, the modulus corresponding conversion corresponding to all moduli smaller than the modulus m _i. The p · 2 ^i-1 bit lower bit string in the first partial sum, which is the sum of the values, is copied as an upper bit string of p · 2 ^i-1 bits higher than the lower bit string, and p · 2 ⁱ bits Generate the addend of
The bit string adding section, said modulus m _i is not the smallest among the plurality of modulus (i = 1, ..., k + 1) for each of the augend for the modulus m _i, to the modulus m _i P · 2 in the second partial sum obtained by adding the partial bit string of the lower p · 2 ⁱ bits in the corresponding conversion value corresponding to the modulus and adding the modulus corresponding conversion value for the modulus to the first partial sum. The conversion apparatus according to claim 1, wherein an ^i- bit lower bit string is calculated.

However, k is an integer greater than or equal to 0, and p is a natural number. The bit string addition unit
For the first modulus m _i1, said p · 2 ⁱ¹ bit augend, and p · 2 ⁱ¹ bit adder for adding said partial bit string of p · 2 ⁱ¹ bits in the modulus corresponding conversion value,
The second of said modulus m _i2, p · 2 ⁱ² of bits of the in augend, and a p · 2 ⁱ² bit adder for adding the partial bit string of p · 2 ⁱ² bits in the modulus corresponding conversion value The conversion device according to claim 3.   The bit string adding unit, when the addition causes an overflow exceeding the number of bits to be added and the number of bits of the partial bit string, a lower bit string having the same number of bits as the number to be added in the bit string obtained as a result of the addition The conversion apparatus according to claim 2, wherein the lower-order bit string of the second partial sum is calculated by adding the bit overflowing to the lower-order bits. A conversion device that converts a converted number expressed by a residue system into a binary number,
The residue system represents the converted number by a set of a plurality of remainder values obtained by dividing the converted number by each of a plurality of moduli,
The first modulus is a value obtained by adding 1 to a power value larger than the product of the modulus less than the first modulus, which is a power of 2 by a natural number,
For each of a plurality of moduli, a modulus corresponding conversion value that is a binary value corresponding to the modulus is generated based on a value obtained by multiplying the remainder of the modulus by a product of a modulus other than the modulus A conversion value generation unit;
A modulus-corresponding conversion value adding unit that adds the modulus-corresponding conversion values for each of the plurality of moduli to calculate the binary converted number;
The modulus corresponding conversion value generation unit
Partial bit string generation for generating a partial bit string that becomes a part of the modulus-corresponding conversion value corresponding to the second modulus based on a bit string of a remainder value obtained by dividing the number of conversion by a second modulus smaller than the first modulus And
A partial bit string duplicating unit that generates the modulus-corresponding conversion value obtained by multiplying the partial bit string by the first modulus by replicating the partial bit string at a plurality of locations of the modulus-corresponding conversion value corresponding to the second modulus. Having a conversion device. The minimum modulus is a natural number of 2 or more obtained by subtracting 1 from a power value of 2 natural numbers;
Each of the non-minimum moduli of the plurality of moduli takes a value obtained by adding 1 to a power value larger than the product of the moduli smaller than the modulus obtained by raising 2 by a natural number,
The partial bit string generation unit is a value obtained by shifting, for each of the non-minimum moduli of a plurality of moduli, a remainder value obtained by the modulus of the converted number to the upper digit side by the number of bits corresponding to the natural number. The conversion apparatus according to claim 6, wherein the partial bit string is generated by subtracting the remainder value from. The plurality of moduli takes the values shown in the following Equation 2,
The partial bit string generation unit, the modulus m _i is not the smallest among the plurality of modulus (i = 1, ..., k + 1) for each of the remainder value by the modulus m _i of the object to be converted number 2 ^i-1 Generate the partial bit string of 2 ⁱ · p bits by subtracting the remainder value from the value shifted to the upper digit side by p bits,
The partial bit string replication unit, for each of the moduli m _i not the minimum and maximum of the plurality of modulus, at a plurality of locations of the modulus corresponding conversion value corresponding to the modulus m ^_i, 2 _i · p bits the partial bit string by replicating at intervals converter according to claim 6, wherein generating the modulus corresponding conversion value corresponding to the modulus m _i.

However, k is an integer greater than or equal to 0, and p is a natural number. The modulus corresponding conversion value generation unit
For the first modulus m _i1, on the basis of the remainder value by said first modulus m _i1 of the number of conversions, a first of said partial bit string generating unit for generating a first of said partial bit string of the 2 ⁱ¹ · p bits ,
For the second modulus m _i2, and on the basis of the remainder value by said first modulus m _i2 of the number of conversions, a second of said partial bit string generating unit for generating a second of said partial bit string of the 2 ⁱ² · p bits ,
A first partial bit string duplicating unit that creates the modulus-corresponding conversion value corresponding to the modulus m _i1 by duplicating the first partial bit string at intervals of 2 ⁱ¹ · p bits;
9. The second partial bit duplicating unit configured to duplicate the second partial bit string at an interval of 2 ⁱ² · p bits to generate the modulus-corresponding conversion value corresponding to the modulus m _i2. 9. Conversion device.

Images