JPS62128334A - Multiplication circuit - Google Patents

Abstract

PURPOSE:To execute a multiplication with a double efficiency in a short time without increasing a circuit scale at all by adding a selection circuit at the periphery of a multiplier of conventional type. CONSTITUTION:A multiplier 1 has the same performance as a conventional type of multiplier which performs multiplication between multipliers K1KN and multiplicands L1-LN and outputs multiplication results M1-M2N-1. A selector 2 is a selector provided at the multiplicand input side of the multiplier 1, and outputs an input A to an output Y when a select input S is 0, and an input B to the output Y when the select input S is 1. 0 is always inputted to the MSB input A of the selector 2, and multiplicands l1-lN are inputted to the input terminal of the selector 2. A selector 3 is a selector provided at the multiplication result output side of the multiplier 1, and similarly as the selector 2, it outputs the input A to the output Y when the select input S is '0', and the input B to the output Y when the select input S is '1'. 0 is always inputted to the LSB input A of the selector 3.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multiplication circuit, and more particularly to a digital multiplication circuit that uses numerical values expressed in two's complement notation.

[Conventional technology]

When performing digital signal processing, one of the important components is a multiplication circuit. In recent years, parallel multiplication circuits that generally have high processing speeds have been widely used. In addition, signal processors dedicated to arithmetic processing with built-in multiplication circuits have appeared, making it possible to perform complex arithmetic processing in real time.

[Problem that the invention seeks to solve]

However, most of the multiplier circuits that are currently widely used have a word length of the multiplier of about 14 to 16 bits, and when performing multiplication with a word length longer than that, it is necessary to perform double precision arithmetic. For signal processors,
Most single-precision multiplications can normally be executed in one instruction cycle, but double-precision multiplications require IO to 20
It takes about a step.

An object of the present invention is to provide a multiplication circuit that can perform double-precision multiplication in a short time without increasing the circuit scale by partially modifying a conventional multiplication circuit that uses two's complement representation. be.

[Means for solving problems]

The multiplication circuit of the present invention outputs M1 to MN4M-1 in two's complement representation of the product of 1 to KN and second input data L1 to L8 to first input data in 2's G city number representation. (here, + and L1M+ respectively represent the least significant bits) and the second input data input side of this multiplier, the most significant bit is given 0, and the most significant bit is included. a first selector that selects the second input data using a first selector; In addition to the output terminal of the second selector, the multiplier has M output terminals to which the most significant bit of the product of the multiplier is output.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

Multiplier 1 multiplies the multiplier by the multiplicands L1-LM (L, LSB, 2's complement) and the multiplicands L1-LM (L, LSB, 2's complement), and produces the multiplication results M1-M2. l-I(Ml
has the same function as a conventional type multiplier that outputs LSB, two's complement representation). Here, LSB is the least significant bit.

Selector 2 is a selector provided on the multiplicand input side of multiplier 1, and when select input S is 0, it outputs Y to the input.
Input B is output to output Y when select input S is 1. The MSB (most significant bit) input A of this selector 2 is always set to 0. The input child of this selector is the multiplicand! , ~b are input. Selector 3 is a selector provided on the multiplication result output side of multiplier 1, and selector 2
Similarly, when select input S is "0", output Y
Input B is output to output Y when select input S is rlJ. The LSB input of this selector 3 is always set to 0.

In explaining the operation of this embodiment, for comparison purposes,
A conventional type multiplier with two's complement representation and an arithmetic logic unit ALU (Arithmet, ic Logic
Let us consider the case where, in a signal processor including unit ), single-precision data F1 to F+ in two's complement representation are multiplied by double-precision data F1 to G2M. First of all, F.

Double-precision multiplication is performed by finding the product of ~F s and G1 ~ GN, and then finding the product of F, ~FN, and 6941 ~ G2N and adding both. At this time, the multiplier calculates the MSB (most F1 to FM and G1 to G in order to determine the upper bit) as the Sign Bit.

When calculating the product, it is necessary to shift G1 to GN to the lower part by 1 bit and put 0 in the MSB. This shift and the operation of putting 0 in the MSB are performed using ΔLU.

Furthermore, since G I - G M is shifted down by 1 bit I at the input, it is necessary to shift the multiplication result up 1 bit to match the scale. The result of the double-precision multiplication is obtained by adding the thus obtained multiplication result and the second calculation, the product of F, ˜F, l and GN−+ −G2g. Of course F1~
FM and 61~Gm bonds are F1~FM and GM+l~02
It is located N bits lower than the product of N. F
1~FM and 61~GW bonds and F, -F, (!:G,,
- When finding the sum of G2's bonds, F, ~FN and G, -
If the bonds of G and I are positive and zero, F, ~FN and 61~
Add N bits of O to the upper part of the product of G8, F1 to F9 and G +
-G If the product of N is negative, F l” F N and G,
~Extend N bits of 1 to the upper part of the product of GN, then F1~
Find the sum of FM and the product of 68°1~G2N. These operations are also performed in separate instruction cycles using ALLI.

In this way, in the case of conventional type signal processors, in order to perform double-precision multiplication, in addition to the instruction cycle that performs two single-precision multiplications and the instruction cycle that calculates the sum of their products, the above-mentioned instruction cycle is used. This requires a large number of operations, and as a result, it takes a lot of time.

Next, the operation of this embodiment will be explained. First, F, ~FN and G
, -G, input F1 to FN to the multiplier inputs of the multiplier circuit and ~KN, and input 61 to GN to the multiplicand inputs β1 to 1 . Enter in I. At this time, the selection signal Sl input to the selection inputs S of selectors 2 and 3
If - is shifted from O, selectors 2 and 3 select input A. Therefore, the inputs L1 to LM of the multiplier l have G, to G
Data is input by shifting N by 1 bit to the lower order and putting 0 in the MSB. The product M which is the multiplication result in multiplier 1
1 to M2M-0 are sent to the selector 3, but since the selector has selected input A, they are shifted one bit upwards, and the products M1 to M211-2 are sent to the outputs 02 to 0 of the selector 3.
2N-1. 0 is output to the output 01 of the selector 3. The most significant bit M2N-1 of the product is output to outputs 028-03N-1 of the multiplier circuit. As mentioned above,
When calculating the product of F1 to F9 and G1 to G, select signal SL
is 0, then the above G, ~G lower shifts and M
Setting 0 to SB, upper shift of multiplication result and upper N
Since bits can be expanded to 0 and 1 in one instruction cycle, the calculation time can be significantly reduced. Next, F
When calculating the product of l-FM and GM+l ~G2N, F
+ -F s is input to the multiplier input of the multiplier circuit from 1 to 8, and G, I+t to G2N is input to the multiplicand input from 11 to 8 of the multiplier circuit.
Enter MN+MN. At this time, selectors 2 and 3
If the selection signal SL input to the selection input S of is 1, selectors 2 and 3 select input B. Therefore, Cz to G2 are input to the inputs L1 to LM of the multiplier 1 as they are.

The product M, ~M2H-1, which is the multiplication result in the multiplier 1, is sent to the selector 3, but since the selector has selected input B, the product M1 ~ M2N-1 is the output 01 of the selector 3.
~0°N-1 is output as is. Furthermore, the most significant pin of the product (M2R-1) is the output 02N~03N of the multiplication circuit.
-1 is output. As mentioned above, F1 to FN and GM.

When calculating the product of 1 to G2N, the selection signal SL may be set to 1. According to this embodiment, the selection signal SL is used as the command word.
Although it is necessary to specify 0 and l, the circuit added around the multiplier 1 is small, as is clear from FIG. 1, and the effect obtained is large in comparison.

〔Effect of the invention〕

As described above, the present invention has the advantage that double precision multiplication can be executed reliably in a short time by simply adding a selection circuit around a conventional type multiplier.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

Claims (2)

[Claims] (1) First input data K_1 to K in two's complement representation
A multiplier that outputs M_1 to M_N_+_M_-_1 in two's complement representation of the product of _N and second input data L_1 to L_M (here, K_1, L_1, and M_1 each represent the least significant bit), and this multiplier a first selector provided on the input side of the second input data of the multiplier, whose most significant bit is given 0, and which selects the second input data including this most significant bit; a second selector provided on the output side, whose least significant bit is given 0 or 1, and selects the product including the least significant bit;
A multiplication circuit comprising, in addition to the output terminal of the second selector, M output terminals from which the most significant bit of the product of the multiplier is output. (2) In the multiplication circuit according to claim 1, when the selection signals to the first and second selectors are on, the second input data L_1 to L_M are shifted one bit lower. Give 0 to the most significant bit and cause the multiplier to output the product M_1 to M_N_+_M_-_1 of the first input data K_1 to K_N, the second input data L_2 to L_M, and the most significant bit 0. , Furthermore, the products M_1 to M_N_+_M_-_1 are shifted to the upper bit by 1 bit, and the least significant bit output O_1 is set to 0 or 1 as the output of the multiplication circuit, and the products M_1 to M_N_+
_M_-_2 is outputted to the outputs O_2 to O_N_+_M_-_1, and the most significant bit M_N_+_ of the product is
Output M_-_1 O_N_+_M ~ O_N_+_2_M
___1, and when the selection signal is off, the product M_1 to M_N_+_M_- of the first input data K_1 to K_N and the second input data L_1 to L_M.
Output _1 to outputs O_1 to O_N_+_M_-_1,
The multiplication circuit further comprises outputting the most significant bit M_N_+_M_-_1 of the product to outputs O_N_+_M to O_N_+_2_M_-_1.