JPS62159224A - Arithmetic circuit for floating point - Google Patents

Abstract

PURPOSE:To reduce the scale of a floating point arithmetic circuit containing an addition/subtraction circuit and a multiplication/division circuit, by using a normalizing circuit of the addition/subtraction circuit when the normalizing process is carried out for multiplication and division. CONSTITUTION:In a circuit 204, high-order 1-bit and zero are added to an exponent part 134 when this part 134 to be normalized is supplied for the normalizing process of multiplication/division. Then the shift number '135' for normalization is subtracted from the part 134 of 8 bits. Thus the normalized 8 bits of the exponent part are obtained and set to a register 115 or 125 which holds the exponent part of a multiplication/division circuit. Thus just a single bit is added to a path used to set said 8 bits to the register 115 and 125 from a register 137. In addition, a small logical change is possible with the circuit 204 since just a single bit is added to the arithmetic. While the mantissa part of multiplication/division undergoes the multiplication and division through a circuit 164 and is set to a register 165.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a floating-point arithmetic circuit, and particularly relates to a floating-point arithmetic circuit suitable for reducing circuit scale. [Background of the Invention] A floating-point arithmetic circuit is , which processes large numbers with high precision. For example, in conventional computers, floating-point numbers consist of three parts: a sign, an exponent, and a mantissa.The exponent is a power of 16, and the mantissa is treated as a hexadecimal number with a decimal point to the left of the most significant digit. ing. Also, floating point numbers that do not contain zero in the hexadecimal digits above the mantissa are called normalized numbers, and subnormal numbers have 1 digit in the high hexadecimal digit of the mantissa.
Contains more than one digit of zero.

In floating-point arithmetic, to convert a subnormal number to a normalized number, the mantissa is shifted to the left until there are no zeros in the most significant digits. The exponent changes by 1 every time the mantissa is shifted by one digit S'j.
will be reduced by This normalization process is also performed when intermediate results are converted to final results, but
In multiplication and division, input data is normalized before the operation is performed.

Floating point arithmetic circuits that operate on such floating point numbers, for example in large computers (M-280H), can be roughly divided into floating point registers, addition/subtraction circuits, and multiplication/division circuits, as shown in Figure 1. has been done.

In the addition/subtraction S\ circuit, the first operand, data 110, read from floating point register 01 is register 11-1, which holds the sign; register 1, which holds the exponent part;
2. Set in the register 13 that holds the mantissa.

Further, the floating point register 01 or the second operand, data 120, read from the memory is set in a register 21 that holds a sign, a register 22 that holds an exponent part, and a register 23 that holds a mantissa part.

The sign in addition and subtraction is determined by the sign of the 1st/2nd operand, the size of their exponent part, etc. 9) This is performed by the circuit 130. The sign of the calculation result is held in the register 31.

For the exponent parts in addition and subtraction, the exponent parts of the 1st and 2nd operands are compared, and if the exponent parts do not match, the mantissa part of the operan with the smaller exponent part is shifted to the right until the two exponent parts are equal. (mantissa digit alignment) is required,
The number of shifts, 133, is calculated. Further, by comparing the exponent parts, the exponent part 134 of the operand having the larger exponent is selected. These are performed by circuit 132.

Further, if an overflow occurs in the intermediate result of addition/subtraction of the mantissa part, 1 is added to the exponent part 134 in order to shift the mantissa part of the intermediate result by one digit to the right.

Also, if normalization is required, shift to the left until there are no high-order zeros in the mantissa of the intermediate result.
The shift number 135 is subtracted from the exponent part 134. These are performed by circuit 136. The exponent part of the calculation result is held in register 137. The mantissa part in the addition/subtraction is input to the small exponent 140 according to the result of the comparison of the exponent part by the circuit 132. Furthermore, the mantissa part of the operand having a large exponent part is input to the T/C circuit 139, and when adding, the data is input as is to the adder 140, and when subtracting, the 1's complement of the input data is taken and added. Vessel 1
Enter 40. The adder 140 adds two pieces of input data, and sends the intermediate result, which is the calculation result, to the circuit 14.
1. 0 circuit 141 that outputs to the shifter 142. Shifter 14
2 is a normalization circuit, and the circuit 141 detects the number of high-order zeros in the input intermediate result, and the intermediate result input to the shifter 142 is determined by the shift number 135, which is the output of the circuit. is shifted to the left. The mantissa part of the operation result is held in the register 143. Addition and subtraction of floating point numbers can be realized by such an addition and subtraction circuit.

In the multiplication/division circuit, first operand data 110 is set in a register 114 that holds a sign, a register 115 that holds an exponent part, and a register 116 that holds a mantissa part. The second operand data 120 is also stored in a register 124 . A register 125 that holds the exponent part. It is set in the register 126 that holds the mantissa.

Normalization processing in multiplication/division requires normalization before multiplication/division is performed, which means that the circuit 150
Registers 116 and 126 that hold the mantissa of the operand
, the number of zeros in the upper digits of either or both mantissa parts is detected, and the shift number 151 for normalization is output. Then, if one or both mantissas contain zero, the selector 152 selects the mantissa that requires normalization, and the shifter 153 shifts the mantissa to the left by a shift number of 151 and holds the mantissa. Set it again in either register 116 or 126. On the other hand, in the denormalization process of the exponent part, the selector 154 selects the exponent of the same operand as the mantissa selected by the selector 152 and inputs it to the adder 155 .

For the other input of the adder, a selector 156 selects the shift number 151 obtained by one circuit 150, and a T/C circuit 157 takes one's complement. Adder 155 adds these two inputs, and sets the result in either register 115 or 125 that holds the exponent part. Based on this principle, when normalization of one operand is completed and both operands require normalization processing, the above processing is repeated. Further, if zero is not detected in either mantissa by the circuit 150, multiplication and division is performed.

The sign in multiplication/division is the sign 11 of the 1st/2nd operand.
4,124, which is performed by one circuit 160, and the sign of the operation result is set in the register 61.

In the case of multiplication by 5, the exponent part in multiplication and division is determined by adding 115 and 126 of the normalized 172nd operand, and in the case of division, it is determined by subtracting them. This process is performed by the T/C circuit 157. This is performed by adder 155. Further, the intermediate result obtained by the above processing requires normalization processing, etc., depending on the intermediate result of the mantissa part, and this is performed by the circuit 162. The exponent part of the calculation result is set in the register 63.

The mantissa part in the multiplication/division is multiplied and divided by the circuit 164. The mantissa part of this operation result is set in the register 165.

A drawback of such floating point arithmetic circuits is that the circuit scale is extremely large.

[Purpose of the invention]

An object of the present invention is to provide a normalization circuit for the addition/subtraction circuit without providing a dedicated normalization circuit for the multiplication/division circuit when performing normalization processing for multiplication/division in a floating point arithmetic circuit having an addition/subtraction circuit and a multiplication/division circuit. The object of the present invention is to provide a floating-point arithmetic circuit that reduces the circuit size by using .

[Summary of the invention]

In the normalization process, only multiplication and division operations require normalization before the operation is performed, and in a program, the operand data that requires normalization before the operation is generally performed is Most of the operand data is normalized.

Therefore, we use an addition/subtraction circuit to normalize the 1st multiplication and division.

This is achieved by inputting the operand data to be normalized for multiplication/division and zero data to the addition/subtraction circuit, performing addition, and normalizing the addition result. This makes it possible to eliminate the normalization circuit of the multiplication/division circuit.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described with reference to FIGS. 2 to 4. Here, to make the explanation easier to understand, I
We will discuss the double-precision floating point data representation of the B Msystem 137Q series and assume that the floating point number is 64 bits.

A floating point number is represented by a 1-bit mantissa sign, a 7-bit exponent, and a 56-bit, or 14-digit mantissa. The mantissa is always expressed in hexadecimal, with the decimal point to the left of the most significant part of the mantissa. The 7 bits of the exponent are 1
It represents a number that should be a power of 6, and the width of the exponent part is -64 to +63, corresponding to binary numbers O to 127.

It consists of a floating point register, 9 addition/subtraction circuits, and 9 multiplication/division circuits.

In this floating point arithmetic circuit, the floating point number is
The first operand data 110 read from 01 is
It is set simultaneously in the registers 111, 112, and 113 of the addition/subtraction circuit and the registers 114, 115, and 116 of the multiplication and division circuit. Similarly, the second operand data read from the floating point register 101 or the memory is similarly set in the registers 121, 122, 123 of the addition/subtraction circuit and the levelsters 124, 125, 126 of the multiplication/division circuit. .

Addition and subtraction are the same as before, and the sign operation is the sign 1 of the 1/2nd operand]1.121. The calculation is performed by the circuit 130 based on the size of the exponent part, etc., and the sign of the calculation result is held in the register 31. The calculation of the exponent part is performed by the circuit 203. The circuit 203 compares the exponent parts of the 1/2 operands and calculates a shift number 133 in order to perform digit alignment of the mantissa parts. Also, depending on the comparison result, the exponent part 134 that is 6-larger is selected.

If overflow or normalization occurs in the intermediate result of the mantissa, the circuit 204 adds 1 to the exponent part 134.
or subtract the shift number 135 for normalization from the exponent part 134. The exponent part of the calculation result is held in register 137. The calculation of the mantissa part is performed by the circuit 20
Based on the comparison result of the exponent part by 3, the mantissa part of the operand having the smaller exponent part is input to the shifter 138 and shifted to the right by the shift number 133. Further, the mantissa part of the operand having a large exponent part is input to the T/C circuit 202, and outputted according to the calculation. These two circuits 138
, 202 are added by an adder 140, and the addition results are input to normalization circuits 141 and 142. The circuit 141 detects the number of high-order zeros in the input addition result, and uses the circuit output, which is the shift number for normalization [35], to shift the addition result input to the shifter 142 to the left. With such a circuit, addition and subtraction of floating point numbers can be realized.

Next, multiplication and division will be explained.

For normalization in multiplication and division, first, the circuit 201
Registers 116 and 126 that hold the mantissa of the operand
Enter the content of and detect whether the regular is required. Since normalization is performed using hexadecimal digits, the normalization detection circuit 201 detects the upper 4 of the mantissa part of the 1st/2nd operand.
All you need to do is look at the bits, and it can be realized with a small circuit. Based on this detection result, if either or both of the first and second operands require normalization, the mantissa part is normalized by the shifter 138 of the addition/subtraction circuit. Inputs the mantissa of the operand and outputs it as is.

Although anything may be input to the other T/C circuit 202,
Its output outputs zero. These outputs are sent to adder 14
0 is input, and the adder 140 performs addition. The addition result is normalized. This is the mantissa part of the operand itself, which is input to normalization circuits 141 and 142. The circuit 141 is a shifter 14 that detects how many zeros there are in the upper part of the mantissa and outputs the shift number 135.
2 shifts the mantissa to be normalized to the left according to the shift number 135. The result is the normalized mantissa,
It is held in register 143.

On the other hand, in the exponent part, the register 112 of the addition/subtraction circuit.
122 is input to the circuit 203, and in the circuit 203, 2
The exponent part 134 of the operand to be normalized is selected from the input exponent parts 112 and 122, and the number of shifts 135 for one-digit alignment is set to zero. By setting the shift number 135 to zero, the shifter 138 can output the input data as is. The selected exponent part 134 is input to the circuit 204, which subtracts the shift number 135 for normalization from the exponent part 134. This result is the normalized exponent part and is stored in register 1.
It is held at 37.

The contents of registers 137 and 143 that hold the normalized exponent and mantissa parts are written to floating point registers in the conventional path, that is, when the result calculated in the previous instruction is used in the next instruction. Registers 115 and 116 or 125 and 12 that hold the exponent part and mantissa part of the 1st/2nd operand data of the multiplication/division circuit are stored using a path 170 provided to eliminate the time required for reading.
Set to either 6. Through such processing,
If normalization of one operand is completed and both operands require normalization, the above process is repeated. Further, in the circuit 201, if neither mantissa part requires normalization, multiplication and division are performed.

Here, the exponent part circuit 204 and the mantissa part normalization circuit 14
In No. 1,142, in the normalization processing of intermediate results of addition and subtraction, when the mantissa part is not zero and the width of the exponent part becomes 165 or less in the normalization, it becomes an interrupt factor of an exponent underflow exception. This is a conventional process, but in the present invention, the multiplication/division normalization process is also performed.
Even if the result of multiplication/division is below, the exponent underflow may not occur, so it is necessary to hold the interrupt factor of the exponent underflow exception until the multiplication/division operation is completed.

Therefore, when the circuit 204 inputs the exponent part 134 to be normalized for normalization processing of multiplication/division, the high-order 1 bit, zero, is added to the exponent part 134 (6), and the 8-bit exponent part from.

By subtracting the shift number 135 for normalization, 8 bits of the normalized exponent part are obtained. As described above, these 8 bits of the normalized exponent part are set in either register 115 or 125 that holds the exponent part of the multiplication/division circuit. It can be seen from the upper bits of registers 115 and 125 that an exponent underflow exception has occurred due to normalization.

When the upper bit is O, it indicates that an exponent underflow exception has not occurred, and when it is 1, it indicates that an exponent underflow exception has occurred.

This process has conventionally been performed in the same way in the normalization circuit of the multiplication circuit, and each register holding the exponent part of the multiplication/division circuit has 8 bits. Therefore, in the present invention, one path is required from the register 137 that holds the normalized exponent part of the addition/subtraction circuit to the register 115 and 125 that holds the exponent part of the squaring/division circuit.
Since the circuit 204 only needs to increase the number of bits, and the circuit 204 performs an operation with an increase of one bit, only a small-scale logic change is required.

Through the above processing, the normalized 172nd operand data is transferred to the registers 114, 115, 116 of the multiplication/division circuit.
and 124, 125, and 126', multiplication and division are performed.

Multiplication and division are the same as before, and the sign of 1 multiplication and division is as follows.

It is determined by the exclusive OR of the signs 114 and 124 of the 1st/2nd operands, which is determined by the circuit 160.
It will be done. What is the sign of the result of that operation?

The exponent part of the 6th multiplication/division set in the register 161 is T/
C circuit 157. The adder 155 adds 115.125 of the normalized 1/2 operand in the case of multiplication, and subtracts them in the case of division. Furthermore, the intermediate result obtained by this processing is subjected to processing such as normalization using the intermediate result of the mantissa part in a circuit 162.

The mantissa part of this operation result is set in the register 163. The mantissa part of the 1 multiplication and division is multiplied and divided by the circuit 164. The mantissa part of this operation result is set in the register 165. With such a circuit, multiplication and division of floating point numbers can be realized.

In FIG. 3, the normalization circuit 2 is
04, 141, and 142, the normalized exponent part and mantissa part are held once in registers 137 and 143, and the exponent part and mantissa part of the multiplication/division circuit are directly held, instead of using the conventional path. Registers 115, 116, 125
, 126, normalization of multiplication and division can be realized.

In addition, in FIG. 4, the exponent part to be normalized for multiplication and division,
Register holding the mantissa part 115゜116.125,1
It is also conceivable to provide paths 401 and 402 for directly inputting the contents of 26 to the normalization circuit of the addition/subtraction circuit, perform normalization, and perform subsequent processing using the method described above.

Furthermore, a method combining the methods shown in FIGS. 3 and 4 is also conceivable.

As described above, according to this embodiment, by performing the normalization of squaring and division using the normalization circuit of the addition and subtraction circuit, the number of normalization circuits of the multiplication and division circuit can be reduced.

〔Effect of the invention〕

According to the present invention, since the normalization of multiplication and division can be performed using the normalization circuit of the addition/subtraction circuit, it is possible to reduce the number of normalization circuits of the 1 multiplication and division circuit.

Furthermore, when implementing a floating-point arithmetic circuit in VLSI, as shown in Figure 2, the wiring area can be reduced by using existing paths without creating new paths for normalizing multiplication and division. This has the effect of reducing the chip area.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a conventional floating point arithmetic circuit, Fig. 2 is a block diagram of a conventional floating point arithmetic circuit that normalizes 1 multiplication and division using a path, Figs. is a block diagram of a floating-point arithmetic circuit that normalizes multiplication and division using each new pass. 201... Normalization detection circuit, 112, 113... Register holding the normalized exponent part and mantissa part of the first operand, 122, 123... Normalized exponent part of the second operand, A register for holding the mantissa, 203.
...Exponent selection and digit alignment calculation circuit, 138...
Shifter for digit alignment of mantissa part, 202... Complement selection circuit, 140... Adder, 204... Normalization circuit of exponent part, 141, 142... Denormalization circuit of mantissa part, 11
5, 116, 125, 126...Registers that hold normalized exponent parts.

Claims (1)

[Claims] For two floating point numbers, exponent calculation is performed by a circuit that selects a larger exponent by comparing the magnitudes of the exponents and calculates the difference, and mantissa calculation is performed by selecting a mantissa having a smaller exponent based on the comparison result. is input into the shifter, and the result of shifting to the right by the difference in exponents and the mantissa with a large exponent are input into a circuit that selects true/complement according to the operation, and the output results are added in an adder. By using the addition/subtraction circuit that calculates addition and subtraction of floating point numbers, and the addition and subtraction circuit that calculates the addition and subtraction of floating point numbers,
In a floating point arithmetic circuit comprising a multiplication/division circuit that calculates floating point multiplication/division by performing subtraction in the case of division using an exponent adder/subtractor that performs subtraction, and performing mantissa calculation in a multiplier/divider that performs multiplication/division, the addition/subtraction circuit From the output of the mantissa, detect the number of high-order zeros in the mantissa, calculate the number of zeros, shift the mantissa to the left by the number of zeros, and from the exponent that is the output of the addition/subtraction circuit. The exponent normalization circuit that subtracts the number of zeros normalizes addition and subtraction, determines whether the upper 4 bits of the mantissas of two floating point numbers are zero, and as a result of that determination, both mantissas are zero. If there is no zero, perform multiplication and division, and if there is zero, use that floating point number as a normalized floating point number, input the normalized floating point number and zero in the addition/subtraction circuit, and add them. The output of the addition/subtraction circuit is the floating point number to be normalized, the multiplication/division is normalized by the mantissa normalization circuit and the exponent normalization circuit, and the result is used to provide a new path. A floating-point arithmetic circuit characterized in that it is desired to store floating-point numbers for multiplication and division in registers that hold floating-point numbers for multiplication and division by paths in which results of addition and subtraction are stored.