JPS6368048U - - Google Patents
Info
- Publication number
- JPS6368048U JPS6368048U JP14988587U JP14988587U JPS6368048U JP S6368048 U JPS6368048 U JP S6368048U JP 14988587 U JP14988587 U JP 14988587U JP 14988587 U JP14988587 U JP 14988587U JP S6368048 U JPS6368048 U JP S6368048U
- Authority
- JP
- Japan
- Prior art keywords
- buffer
- digits
- result
- calculation
- stores
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 208000003580 polydactyly Diseases 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 1
Description
第１図はバツク形式の数字を示す図、第２図は
従来の演算過程を説明するための図、第３図は本
考案の一実施例を説明する図、第４図は第３図を
実施するための具体的構成図である。
１，２……第１バツフア、３，４，５，６……
乗算器、７，８，９，１０……第２のバツフア、
１１……加算器、１２……バツフア、１３，１４
……第１の加算手段（加算器）、１５，１６……
第３のバツフア、１７……第４のバツフア、１８
……第２の加算手段（加算器）、１９……第５の
バツフア、２０，２１……バツフア、２２……加
算器、２３……バツフア。
Figure 1 is a diagram showing numbers in back format, Figure 2 is a diagram to explain the conventional calculation process, Figure 3 is a diagram to explain an embodiment of the present invention, and Figure 4 is a diagram showing Figure 3. It is a concrete block diagram for implementation. 1, 2...1st battle, 3, 4, 5, 6...
Multiplier, 7, 8, 9, 10...second buffer,
11... Adder, 12... Buffer, 13, 14
...First addition means (adder), 15, 16...
Third battle, 17...Fourth battle, 18
... second addition means (adder), 19 ... fifth buffer, 20, 21 ... buffer, 22 ... adder, 23 ... buffer.
Claims (1)
、 被乗数、乗数を予め決められた複数桁単位に格
納される第１のバツフアと、 該第１のバツフアに格納された値の各桁の組み
合わせをそれぞれに演算する演算手段と、 該演算手段の演算結果を格納する複数個の第２
のバツフアと、 該第２のバツフアに格納された演算結果を予め
決められた組み合わせにより加算するための第１
の加算手段と、 該第１の加算手段の結果を上位桁と下位桁に分
けてそれぞれ格納する第３のバツフアと、 該下位桁を格納した第３のバツフアの値を退避
して格納する第４のバツフアと、 先の演算結果を退避してある第４のバツフアの
値と、次の前記演算手段および第１の加算手段に
より演算した結果の上位桁とを加算する第２の加
算手段と、 第２の加算手段による加算結果を上位桁に、第
１の加算手段の加算結果の上位桁の値を下位桁に
それぞれ格納することで演算結果を格納する第５
のバツフアとを備えたこと を特徴とする演算装置。[Claims for Utility Model Registration] A device for calculating multiplicands and multipliers in pack format, comprising a first buffer in which the multiplicand and multiplier are stored in predetermined units of multiple digits; a calculation means for calculating each combination of digits of the value, and a plurality of second units for storing the calculation results of the calculation means.
buffer and the calculation result stored in the second buffer by a predetermined combination.
a third buffer that divides the result of the first addition means into high-order digits and low-order digits and stores them, respectively; and a third buffer that saves and stores the value of the third buffer that stores the low-order digits. 4 buffer, a second adding means for adding the value of the fourth buffer in which the previous calculation result is saved, and the upper digit of the result calculated by the next calculation means and the first addition means; , a fifth section that stores the calculation result by storing the addition result by the second addition means in the upper digits and the value of the upper digit of the addition result by the first addition means in the lower digits, respectively.
An arithmetic device characterized by having a buffer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14988587U JPS6368048U (en) | 1987-09-30 | 1987-09-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14988587U JPS6368048U (en) | 1987-09-30 | 1987-09-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6368048U true JPS6368048U (en) | 1988-05-07 |
Family
ID=31065514
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14988587U Pending JPS6368048U (en) | 1987-09-30 | 1987-09-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6368048U (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5289435A (en) * | 1976-01-22 | 1977-07-27 | Mitsubishi Electric Corp | Multiplying device |
| JPS5345948A (en) * | 1976-10-07 | 1978-04-25 | Nippon Telegr & Teleph Corp <Ntt> | Multiplier circuit |
| JPS5386135A (en) * | 1977-01-07 | 1978-07-29 | Nippon Hoso Kyokai <Nhk> | High-speed multiplier |
| JPS56149642A (en) * | 1980-04-21 | 1981-11-19 | Fujitsu Ltd | Multiplier |
-
1987
- 1987-09-30 JP JP14988587U patent/JPS6368048U/ja active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5289435A (en) * | 1976-01-22 | 1977-07-27 | Mitsubishi Electric Corp | Multiplying device |
| JPS5345948A (en) * | 1976-10-07 | 1978-04-25 | Nippon Telegr & Teleph Corp <Ntt> | Multiplier circuit |
| JPS5386135A (en) * | 1977-01-07 | 1978-07-29 | Nippon Hoso Kyokai <Nhk> | High-speed multiplier |
| JPS56149642A (en) * | 1980-04-21 | 1981-11-19 | Fujitsu Ltd | Multiplier |
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