JPS58124831U

JPS58124831U - decimal calculator

Info

Publication number: JPS58124831U
Application number: JP2157082U
Authority: JP
Inventors: 谷口　俊久
Original assignee: 株式会社日立製作所
Priority date: 1982-02-19
Filing date: 1982-02-19
Publication date: 1983-08-25

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of drawings]

第１図は、従来の＋６．−６回路付十進加減算器のブロ
ック図、第２図は０から９迄をそれぞれ加算した結果を
示す図、第３図はＡ＋Ｂの結果キャリーがプ０／マゲー
トされる領域を示す図、第４図はＡ＋Ｂの結果キャリー
がジェネレートされる領域を示す図、第５〜８図は、そ
れぞれ２３．　２２゜２１．２°ビツトが立つ加算の組
合せを示す図、第９〜１５図は、減算の場合を示す図、
第１６図は、本考案の実施例のブロック図、第１７図は
第１６図３の補正回路図、第１８図は従来の＋６回路付
十進加算器におけるキャリープロパゲータ、キャーリー
ジエネレータ回路図、第１９図は、本考案におけるキャ
リープロパゲータの回路図、第２０図は、キャリージェ
ネレータの回路図、第２１図は、第１６図の４ビツト加
算器で２バイト加算器を構成した時のブロック図である
。１・・・４ビツト入力をデコードする回路、２・・・加
算結果を生成する回路、３・・・補正回路、４・・・キ
ャリー、５，６・・・２バイトレジスタ、８・・・補正
回路、９・・・２バイトレジスタ。才２図　　　　　　葎３　図　　　　　　　ｆ４回＋戊　則ＩＩ＋　　　　、１−−−−−−ｔｌｉ　　　　　１−
６６６６ −Ｏｏ　　Ｄｔ　　−Ｕ２　　σ３才　Ｉ７閉Figure 1 shows the conventional +6. - A block diagram of a decimal adder/subtractor with 6 circuits. Figure 2 is a diagram showing the results of adding each number from 0 to 9. Figure 3 is a diagram showing the area where the result carry of A+B is pre-0/magated. Figure 4 is a diagram showing the area where a carry is generated as a result of A+B, and Figures 5 to 8 are respectively 23. Figures 9 to 15 are diagrams showing combinations of addition where the 22° and 21.2° bits are set, and Figures 9 to 15 are diagrams showing subtraction.
Fig. 16 is a block diagram of an embodiment of the present invention, Fig. 17 is a correction circuit diagram of Fig. 16 3, and Fig. 18 is a carry propagator and carry generator circuit diagram in a conventional decimal adder with +6 circuit. , FIG. 19 is a circuit diagram of the carry propagator in the present invention, FIG. 20 is a circuit diagram of a carry generator, and FIG. 21 is a block diagram when a 2-byte adder is configured with the 4-bit adder of FIG. 16. It is a diagram. 1...Circuit for decoding 4-bit input, 2...Circuit for generating addition result, 3...Correction circuit, 4...Carry, 5, 6...2-byte register, 8... Correction circuit, 9...2-byte register. Sai 2 Figure 葎 3 Figure f4 times + 戊 RU II + , 1------tli 1-
6666 -Oo Dt -U2 σ3 years old I7 closed

Claims

[Scope of utility model registration request]

For two decimalized 4-bit inputs, it has two decoders with outputs corresponding to their values from 0 to 9, and from each combination of the outputs of the two decoders A decimal arithmetic unit characterized by having a circuit for generating addition/subtraction results, a carry propagator, and a carry generator.