JPS59128633A - One-chip microcomputer - Google Patents

Abstract

PURPOSE:To obtain an one-chip microcomputer saving the number of instruction steps and execution time by providing the 1st and 2nd adders and a constant generating circuit. CONSTITUTION:Two 4-bit inputs to a 4-bit binary adder 1 are 10-A3, B0-B3 respectively and a carrying input 1a selects a binary carrying signal 5a and a decimal carrying signal 6a by a carry selecting gate 4. The added results of an adder 8 are outputted as 4-bit added result outputs C0-C3 and a carrying output signal 1b. A constant circuit 3 inputs a carrying signal 1b, added results C1- C3 and control signals 3a, 3b and outputs constant outputs D1-D3 and a decimal carrying signal 3c. An adder 2 inputs added results C0-C3 outputted from the adder 1 and constant outputs D1-D3 of the constant generating circuit 3 and outputs binary-coded decimal outputs E0-E3 of the added results.

Description

[Detailed description of the invention] The present invention relates to a one-chip microcomputer.

In a conventional one-chip microcomputer, after performing addition and subtraction of two rounds, the zero evolution correction is performed, which increases the number of instruction steps and the execution time.

SUMMARY OF THE INVENTION An object of the present invention is to provide a one-chip microcomputer with a simple circuit configuration that saves the number of instruction steps and execution time.

FIG. 1 shows an embodiment of a one-digit binary addition/decimal adder/subtractor according to the present invention, where 1 is a first adder, 2 is a second adder, and 3 is a constant generation circuit.

The two 4-bit inputs of the first 4-bit binary adder 1 are respectively A. -A, , Bo-B, and the carry input 1α can select either the binary carry signal 5α or the decimal carry signal 6α by the carry selection gate 4.

4α is a binary carry selection signal, and 4b is a decimal carry selection signal. 8 are full adders, and the addition results of these inputs are output as 4-bit addition result outputs 00-03 and a carry output signal 1h. The constant generation circuit 3 outputs a carry output signal 1h and addition result outputs 01 to O3.
It inputs the addition control signal 3α and the subtraction control signal 3b, and outputs constant outputs D1 to D3 and a decimal carry output signal 3C as shown in Table 1. In this embodiment, the 2° bit is omitted, but since the second adder 2 handles the 20 bits as '0#', the constant outputs D1 to D are the hexadecimal value '0'. #, “6”, “
Corresponds to A#.

The second adder 2 receives the 4-bit addition result output Oo~03 of the first adder 1 and the constant output D1 of the constant generation circuit 3.
~D3 is input, and the addition result is the binary coded decimal power KO-
Outputs H.

The decimal carry output signal 3C is input to the latch 6, and the carry output signal 1b is input to the latch 5, and is latched by the clock signal 7 generated at an appropriate timing. The output of the latch 5 is a binary carry signal 5a, and the output of the latch 6 is a decimal carry signal 6α, which are connected to the gate inputs of the carry selection gate 4, respectively. This makes it possible to add and subtract multi-digit decimal numbers through repeated operations.

FIG. 2 shows a second embodiment of the present invention, and is an example in which two binary addition/decimal adder/subtractors are connected to form two digits.

As described above, according to the present invention, the inconvenience of processing decimal addition/subtraction and decimal evolution correction separately is solved, and the processing is performed all at once by executing the instructions twice, thereby saving instruction steps and execution time. . Also, AO””” m e
”0- Sets one value of two 4-bit inputs of Bl to 1.
If the hexadecimal value is "0", a binary number can be converted to a decimal number using the same procedure as the addition process, and the number of types of instructions can be reduced.

[Brief explanation of drawings]

FIG. 1 shows an embodiment of a one-digit binary addition decimal adder/subtractor of the present invention, and FIG. 2 shows an embodiment of a two-digit binary addition decimal adder/subtractor of the present invention. 1 and 1' are the first adders, 2 and 2' are the second adders, 3
and 3' are constant generation circuits, 4 and 4' are carry selection gates, 5 and 6 are latches, Oo to 0. 1b is a carry output signal, 3α is an addition control signal, 5b is a subtraction control signal, and 5c is a decimal carry output signal.

Claims (1)

[Claims] A 4-bit binary adder is used as the first adder, and the 4-bit 2
Three types of 16 blood values are generated by the addition result output of the decimal adder, the carry output signal, the addition control signal, and the subtraction control signal.
'0''tl#,IIA#, and a constant generation circuit that appropriately generates a decimal carry output signal;
A 1-digit binary addition decimal adder/subtractor consisting of a second adder that adds the addition result output of the 4-bit binary adder and a constant output of the constant generating circuit is connected to form a digit number. I did 2
A one-chip microcomputer characterized by having a decimal adder/subtractor.