JPH0464828U - - Google Patents
Info
- Publication number
- JPH0464828U JPH0464828U JP10788090U JP10788090U JPH0464828U JP H0464828 U JPH0464828 U JP H0464828U JP 10788090 U JP10788090 U JP 10788090U JP 10788090 U JP10788090 U JP 10788090U JP H0464828 U JPH0464828 U JP H0464828U
- Authority
- JP
- Japan
- Prior art keywords
- multiplier
- decoder
- circuit
- selector
- value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000005540 biological transmission Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Complex Calculations (AREA)
- Error Detection And Correction (AREA)
Description
第１図……本考案の畳み込み演算回路用乗算器
、第２図……本考案で使用する乗数デコーダとセ
レクタの構成を示す図、第３図……２進数Ａ，Ｂ
の通常の乗算の仕方を示す図、第４図……２進数
を下位より２ビツトづつ区切る図、第５図……本
考案で使用するアルゴリズムを示す図、第６図…
…本考案を適用した転置型トランスバーサルフイ
ルタ、第７図……従来の畳み込み演算回路用乗算
器、第８図……従来の畳み込み演算回路用乗算器
に使用していた乗算デコーダとセレクタの構成を
示す図、第９図……変形ブースのアルゴリズムを
示す図、第１０図……従来の転置型トランスバー
サルフイルタ。
図において、１は乗数入力部、２は乗数デコー
ダ、３は乗数デコーダ部、４は被乗数入力端子、
５はセレクタ、６は加算器、７は出力端子、８は
乗数ビツト入力端子、９はセレクト信号線、１０
はセレクタ出力端子、１１は３倍回路、１２は被
乗数入力端子、１３はラツチ、１４−１，１４−
２，１４−３は乗算器、１５−１，１５−２は加
算器、１６は出力端子、３０〜３３は乗算結果、
５１はトランスミツシヨンゲート、５２はトラン
ジスタ、５３はインバータ、５４はＡＮＤ／ＮＯ
Ｒ回路、５６はイクスクルーシブＯＲ回路である
。
Figure 1: Multiplier for convolution arithmetic circuit of the present invention; Figure 2: Diagram showing the structure of the multiplier decoder and selector used in the present invention; Figure 3: Binary numbers A, B
Figure 4 shows how to normally multiply... Figure 5 shows how to divide a binary number into two bits from the lowest order... Figure 6 shows the algorithm used in this invention...
...Transposed type transversal filter to which the present invention is applied, Fig. 7... Conventional multiplier for convolution arithmetic circuit, Fig. 8... Configuration of multiplication decoder and selector used in conventional multiplier for convolution arithmetic circuit. FIG. 9 shows a modified Booth algorithm. FIG. 10 shows a conventional transposed transversal filter. In the figure, 1 is a multiplier input section, 2 is a multiplier decoder, 3 is a multiplier decoder section, 4 is a multiplicand input terminal,
5 is a selector, 6 is an adder, 7 is an output terminal, 8 is a multiplier bit input terminal, 9 is a select signal line, 10
is a selector output terminal, 11 is a triple circuit, 12 is a multiplicand input terminal, 13 is a latch, 14-1, 14-
2 and 14-3 are multipliers, 15-1 and 15-2 are adders, 16 is an output terminal, 30 to 33 are multiplication results,
51 is a transmission gate, 52 is a transistor, 53 is an inverter, 54 is an AND/NO
The R circuit 56 is an exclusive OR circuit.
Claims (1)
路と、乗数Ｂの最下位ビツトより２ビツトづつ区
切つた各２ビツトに対応して設けられ、該２ビツ
トが入力され且つそれらの値の組み合わせの種類
を判別する乗数デコーダと、該乗数デコーダに対
応して設けられ、前記乗数デコーダからの判別信
号に応じて０，Ａ，２Ａまたは３Ａのいずれかの
値を選択して出力するセレクタと、該セレクタの
出力を適宜シフトさせて加算する加算器とを具え
たことを特徴とする畳み込み演算回路用乗算器。 A 3x circuit outputs a value (3A) that is 3 times the multiplicand A, and a 3x circuit is provided corresponding to each 2 bits separated by 2 bits starting from the least significant bit of the multiplier B. a multiplier decoder that determines the type of combination; and a selector provided corresponding to the multiplier decoder that selects and outputs a value of 0, A, 2A, or 3A in accordance with a determination signal from the multiplier decoder. 1. A multiplier for a convolution arithmetic circuit, comprising: and an adder that appropriately shifts and adds the output of the selector.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10788090U JP2524035Y2 (en) | 1990-10-15 | 1990-10-15 | Multiplier for convolution arithmetic circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10788090U JP2524035Y2 (en) | 1990-10-15 | 1990-10-15 | Multiplier for convolution arithmetic circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0464828U true JPH0464828U (en) | 1992-06-04 |
| JP2524035Y2 JP2524035Y2 (en) | 1997-01-29 |
Family
ID=31854596
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10788090U Expired - Lifetime JP2524035Y2 (en) | 1990-10-15 | 1990-10-15 | Multiplier for convolution arithmetic circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2524035Y2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2021152703A (en) * | 2020-03-24 | 2021-09-30 | 株式会社東芝 | Neural network apparatus and neural network system |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP7183079B2 (en) | 2019-03-08 | 2022-12-05 | 株式会社東芝 | semiconductor equipment |
-
1990
- 1990-10-15 JP JP10788090U patent/JP2524035Y2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2021152703A (en) * | 2020-03-24 | 2021-09-30 | 株式会社東芝 | Neural network apparatus and neural network system |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2524035Y2 (en) | 1997-01-29 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |