JPS553066A - Composite multiplier - Google Patents

Composite multiplier

Info

Publication number
JPS553066A
JPS553066A JP7572678A JP7572678A JPS553066A JP S553066 A JPS553066 A JP S553066A JP 7572678 A JP7572678 A JP 7572678A JP 7572678 A JP7572678 A JP 7572678A JP S553066 A JPS553066 A JP S553066A
Authority
JP
Japan
Prior art keywords
multiplier
multipliers
output
unit
digit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7572678A
Other languages
Japanese (ja)
Inventor
Kenji Nakayama
Toshihiko Mizukami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP7572678A priority Critical patent/JPS553066A/en
Publication of JPS553066A publication Critical patent/JPS553066A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To give the flexibility to the system design by realizing such multiplier that comprises N-units of multipliers and can be used as one unit of the multiplier as a whole or as several units of multipliers according to the coefficient word length.
CONSTITUTION: N-unit multiplicand X and multiplier A are multiplied each other in N-unit multipliers to obtain N-unit output Y, and at the same time the output of the multiplier has the digit shift with an addition possible with the output having no digit shift. Thus a larger digit number can be applied for the multiplier. Furthermore, an addition is given with the output of other multipliers or adders by giving the digit shift to the addition output, and thus the digit number can be increased more for the multiplier. In that case, the same multiplier is given to the multipliers which perform multiplication simultaneously. Several multipliers are combined according to the digit number of the multiplier to obtain the output, and then several multiplications become possible at one time with combinations of multipliers.
COPYRIGHT: (C)1980,JPO&Japio
JP7572678A 1978-06-21 1978-06-21 Composite multiplier Pending JPS553066A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7572678A JPS553066A (en) 1978-06-21 1978-06-21 Composite multiplier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7572678A JPS553066A (en) 1978-06-21 1978-06-21 Composite multiplier

Publications (1)

Publication Number Publication Date
JPS553066A true JPS553066A (en) 1980-01-10

Family

ID=13584552

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7572678A Pending JPS553066A (en) 1978-06-21 1978-06-21 Composite multiplier

Country Status (1)

Country Link
JP (1) JPS553066A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56101266A (en) * 1980-01-18 1981-08-13 Nec Corp Processor for signal processing
JPS58132862A (en) * 1982-01-30 1983-08-08 Sairatsuku:Kk Coordinate converting circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56101266A (en) * 1980-01-18 1981-08-13 Nec Corp Processor for signal processing
JPH0127463B2 (en) * 1980-01-18 1989-05-29 Nippon Electric Co
JPS58132862A (en) * 1982-01-30 1983-08-08 Sairatsuku:Kk Coordinate converting circuit

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