JPS576972A - Multiplying circuit of complex number - Google Patents
Multiplying circuit of complex numberInfo
- Publication number
- JPS576972A JPS576972A JP8181280A JP8181280A JPS576972A JP S576972 A JPS576972 A JP S576972A JP 8181280 A JP8181280 A JP 8181280A JP 8181280 A JP8181280 A JP 8181280A JP S576972 A JPS576972 A JP S576972A
- Authority
- JP
- Japan
- Prior art keywords
- circuits
- time
- supplied
- real
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06G—ANALOGUE COMPUTERS
- G06G7/00—Devices in which the computing operation is performed by varying electric or magnetic quantities
- G06G7/12—Arrangements for performing computing operations, e.g. operational amplifiers
- G06G7/16—Arrangements for performing computing operations, e.g. operational amplifiers for multiplication or division
- G06G7/161—Arrangements for performing computing operations, e.g. operational amplifiers for multiplication or division with pulse modulation, e.g. modulation of amplitude, width, frequency, phase or form
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Theoretical Computer Science (AREA)
- Power Engineering (AREA)
- Software Systems (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Complex Calculations (AREA)
Abstract
PURPOSE:To reduce the number of multiplying circuits, by arranging in time-division within the unit computing time for both the real and imaginary number parts of a multiplicand. CONSTITUTION:The real number part (a) and the imaginary number part (b) of the multiplicant of the complex number supplied the input terminals 1 and 2 are arrayed in time division and within the unit arithmetic time (s) through a time dividing circuit 20 and with a timing T1. The output of the circuit 20 is supplied to the 1st and 2nd multiplying circuits 7 and 8 as a multiplicand respectively. While the real number part (c) and the imaginary number part (d) of the multiplier of the complex number supplied through input terminals 3 and 4 are supplied to the circuits 7 and 8 respectively. A multiplication is carried out between the parts (c) and (d) of the multiplicand and multiplier arrayed in time division through the circuits 7 and 8 to obtain products (e) and (f). These products (e) and (f) are delayed through delaying circuits 21 and 22 and by 1/2 unit computing time interval to deliver products e' and f'. A subtraction is carried out between e' and (f) through a subtracting circuit 11, and an addition is carried out through an adding circuit between (e) and f' to obtain a difference (g) and sum (h). Both (g) and (h) are latched by latching circuits 13 and 14 to obtain both the real and imaginary number parts of the product of a complex number.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8181280A JPS576972A (en) | 1980-06-16 | 1980-06-16 | Multiplying circuit of complex number |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8181280A JPS576972A (en) | 1980-06-16 | 1980-06-16 | Multiplying circuit of complex number |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS576972A true JPS576972A (en) | 1982-01-13 |
Family
ID=13756902
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8181280A Pending JPS576972A (en) | 1980-06-16 | 1980-06-16 | Multiplying circuit of complex number |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS576972A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62194577A (en) * | 1985-12-16 | 1987-08-27 | テキサス インスツルメンツ インコ−ポレイテツド | Complex multiplier and complex multiplication |
JPH01296707A (en) * | 1988-05-24 | 1989-11-30 | Sony Corp | Digital arithmetic circuitry |
WO1999000746A1 (en) * | 1997-06-26 | 1999-01-07 | Asahi Kasei Kogyo Kabushiki Kaisha | Parallel arithmetic units and digital signal processor using the same |
CN112748898A (en) * | 2021-02-14 | 2021-05-04 | 成都启英泰伦科技有限公司 | Complex vector computing device and computing method |
-
1980
- 1980-06-16 JP JP8181280A patent/JPS576972A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62194577A (en) * | 1985-12-16 | 1987-08-27 | テキサス インスツルメンツ インコ−ポレイテツド | Complex multiplier and complex multiplication |
JPH01296707A (en) * | 1988-05-24 | 1989-11-30 | Sony Corp | Digital arithmetic circuitry |
WO1999000746A1 (en) * | 1997-06-26 | 1999-01-07 | Asahi Kasei Kogyo Kabushiki Kaisha | Parallel arithmetic units and digital signal processor using the same |
CN112748898A (en) * | 2021-02-14 | 2021-05-04 | 成都启英泰伦科技有限公司 | Complex vector computing device and computing method |
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