JPS5752959A - Multiplier - Google Patents

Multiplier

Info

Publication number
JPS5752959A
JPS5752959A JP55126798A JP12679880A JPS5752959A JP S5752959 A JPS5752959 A JP S5752959A JP 55126798 A JP55126798 A JP 55126798A JP 12679880 A JP12679880 A JP 12679880A JP S5752959 A JPS5752959 A JP S5752959A
Authority
JP
Japan
Prior art keywords
number part
output
product
outputs
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55126798A
Other languages
Japanese (ja)
Other versions
JPS6156823B2 (en
Inventor
Haruo Akagi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP55126798A priority Critical patent/JPS5752959A/en
Publication of JPS5752959A publication Critical patent/JPS5752959A/en
Publication of JPS6156823B2 publication Critical patent/JPS6156823B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/4806—Computations with complex numbers
    • G06F7/4812—Complex multiplication

Abstract

PURPOSE:To reduce in size and electric power comsumption, by performing multiplying of complex number after subjecting both multiplicands and multipliers to time-division arrangement. CONSTITUTION:An output a/b is obtained by making a time division arrangement 20 on a real number part (a) and an imaginary number part (b) of an input 1 and 2 multiplicant. On the other hand, outputs c/d and d/c are obtained by making another time division arrangement 21 on a real number part (c) and an imaginary number part (d). At the first multiplying circuit 7 and 8, products (e) and (f) are output from the above mentioned outputs. Moreover, at delaying circuits 22 and 23, outputs e1 and f1 are obtained by delaying these products (e) and (f). At a subtracting circuit 11, a difference (g) is obtained by subtracting the product (e) from this output e1, and, at an adding circuit 12, a sum (h) is obtained by adding the product (f) to the output f1. At latch circuits 13 and 14, a real number part and an imaginary number part of the product of complex numbers are obtained by latching the difference (g) and the sum (h).
JP55126798A 1980-09-11 1980-09-11 Multiplier Granted JPS5752959A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55126798A JPS5752959A (en) 1980-09-11 1980-09-11 Multiplier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55126798A JPS5752959A (en) 1980-09-11 1980-09-11 Multiplier

Publications (2)

Publication Number Publication Date
JPS5752959A true JPS5752959A (en) 1982-03-29
JPS6156823B2 JPS6156823B2 (en) 1986-12-04

Family

ID=14944207

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55126798A Granted JPS5752959A (en) 1980-09-11 1980-09-11 Multiplier

Country Status (1)

Country Link
JP (1) JPS5752959A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58223846A (en) * 1982-06-23 1983-12-26 Fujitsu Ltd Multiplier of complex number
WO1999000746A1 (en) * 1997-06-26 1999-01-07 Asahi Kasei Kogyo Kabushiki Kaisha Parallel arithmetic units and digital signal processor using the same
KR100433627B1 (en) * 2001-12-11 2004-05-31 한국전자통신연구원 Low power multiplier for complex numbers
WO2021157172A1 (en) * 2020-02-06 2021-08-12 三菱電機株式会社 Complex multiplication circuit

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0424889Y2 (en) * 1986-05-30 1992-06-12

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58223846A (en) * 1982-06-23 1983-12-26 Fujitsu Ltd Multiplier of complex number
WO1999000746A1 (en) * 1997-06-26 1999-01-07 Asahi Kasei Kogyo Kabushiki Kaisha Parallel arithmetic units and digital signal processor using the same
KR100433627B1 (en) * 2001-12-11 2004-05-31 한국전자통신연구원 Low power multiplier for complex numbers
WO2021157172A1 (en) * 2020-02-06 2021-08-12 三菱電機株式会社 Complex multiplication circuit

Also Published As

Publication number Publication date
JPS6156823B2 (en) 1986-12-04

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