JPS57157351A - Operating circuit - Google Patents

Operating circuit

Info

Publication number
JPS57157351A
JPS57157351A JP4342381A JP4342381A JPS57157351A JP S57157351 A JPS57157351 A JP S57157351A JP 4342381 A JP4342381 A JP 4342381A JP 4342381 A JP4342381 A JP 4342381A JP S57157351 A JPS57157351 A JP S57157351A
Authority
JP
Japan
Prior art keywords
square
sets
multiplier
data
integer data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4342381A
Other languages
Japanese (ja)
Inventor
Kenichi Miura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP4342381A priority Critical patent/JPS57157351A/en
Publication of JPS57157351A publication Critical patent/JPS57157351A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/552—Powers or roots, e.g. Pythagorean sums

Abstract

PURPOSE:To enable to operate square or mutual products in parallel, as to (n) sets of data in using a single multiplier, by providing a specific input multiplexer, a multiplier, and an output multiplexer respectively. CONSTITUTION:An input multiplexer 2 which interpolates a predetermined data including zero between given (n) sets of non-minus integer data (e.g., A-C) so that no interference is caused between square values of the result of multiplication and/or mutual products, is provided. Further, a multiplier(e.g., a square device) 4 which multiplies (n) sets of non-munus integer data interpolated with the said predetermined data and an output multiplexer 7 which separately picks up the square or mutual products of the non-minus integer data as a result of the operation of the multiplier 4, are provided. Thus, the square and/or mutual products as to the (n) sets of non-minus integer data are operated in parallel.
JP4342381A 1981-03-25 1981-03-25 Operating circuit Pending JPS57157351A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4342381A JPS57157351A (en) 1981-03-25 1981-03-25 Operating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4342381A JPS57157351A (en) 1981-03-25 1981-03-25 Operating circuit

Publications (1)

Publication Number Publication Date
JPS57157351A true JPS57157351A (en) 1982-09-28

Family

ID=12663283

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4342381A Pending JPS57157351A (en) 1981-03-25 1981-03-25 Operating circuit

Country Status (1)

Country Link
JP (1) JPS57157351A (en)

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