JPS57199044A - Multiplying device - Google Patents
Multiplying deviceInfo
- Publication number
- JPS57199044A JPS57199044A JP56085098A JP8509881A JPS57199044A JP S57199044 A JPS57199044 A JP S57199044A JP 56085098 A JP56085098 A JP 56085098A JP 8509881 A JP8509881 A JP 8509881A JP S57199044 A JPS57199044 A JP S57199044A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- adder
- output
- sum
- addition
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
- G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
- G06F7/5324—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel partitioned, i.e. using repetitively a smaller parallel parallel multiplier or using an array of such smaller multipliers
Abstract
PURPOSE:To simplify a Wallace tree circuit to make the operation cycle high- speed, by inputting the carry and the sum of the Wallace tree circuit to an adder and adding them to the preceding output of the adder to obtain a product value and performing only the addition of partial products in the tree circuit. CONSTITUTION:A multiplier 12 and a multiplicand 10 are multiplied in a multiplying circuit 14, and an output A is applied to a Wallace tree circuit 16, and a carry output B' and a sum output C' from the circuit 16 are applied to an adder 26. A part F (lower 2 bits omitted) of the preceding addition output from a register 28 is inputted to the adder 26. The preceding output and the carry output B' and the sum output C' from the circuit 16 are added in the adder 26 to obtain a product value, and only the addition of partial products is performed in the circuit 26, and integral products and partial product results are adder in the adder 26, thus simplifying the circuit 16 to make the operation cycle high-speed.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56085098A JPS57199044A (en) | 1981-06-03 | 1981-06-03 | Multiplying device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56085098A JPS57199044A (en) | 1981-06-03 | 1981-06-03 | Multiplying device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57199044A true JPS57199044A (en) | 1982-12-06 |
Family
ID=13849129
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56085098A Pending JPS57199044A (en) | 1981-06-03 | 1981-06-03 | Multiplying device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57199044A (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60144826A (en) * | 1984-01-05 | 1985-07-31 | Nec Corp | Arithmetic processor |
US4852037A (en) * | 1986-08-16 | 1989-07-25 | Nec Corporation | Arithmetic unit for carrying out both multiplication and addition in an interval for the multiplication |
JPH0247769A (en) * | 1988-08-09 | 1990-02-16 | Matsushita Electric Ind Co Ltd | Product sum arithmetic unit |
US5138574A (en) * | 1986-09-17 | 1992-08-11 | Fujitsu Limited | Method and device for obtaining sum of products using integrated circuit |
JPH06110659A (en) * | 1992-06-30 | 1994-04-22 | Nec Corp | Microcomputer |
US7313585B2 (en) | 2003-08-30 | 2007-12-25 | Hewlett-Packard Development Company, L.P. | Multiplier circuit |
-
1981
- 1981-06-03 JP JP56085098A patent/JPS57199044A/en active Pending
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60144826A (en) * | 1984-01-05 | 1985-07-31 | Nec Corp | Arithmetic processor |
US4852037A (en) * | 1986-08-16 | 1989-07-25 | Nec Corporation | Arithmetic unit for carrying out both multiplication and addition in an interval for the multiplication |
US5138574A (en) * | 1986-09-17 | 1992-08-11 | Fujitsu Limited | Method and device for obtaining sum of products using integrated circuit |
JPH0247769A (en) * | 1988-08-09 | 1990-02-16 | Matsushita Electric Ind Co Ltd | Product sum arithmetic unit |
JPH06110659A (en) * | 1992-06-30 | 1994-04-22 | Nec Corp | Microcomputer |
US7313585B2 (en) | 2003-08-30 | 2007-12-25 | Hewlett-Packard Development Company, L.P. | Multiplier circuit |
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