JPS6476162A - Arithmetic circuit for sum of products - Google Patents

Arithmetic circuit for sum of products

Info

Publication number
JPS6476162A
JPS6476162A JP23332687A JP23332687A JPS6476162A JP S6476162 A JPS6476162 A JP S6476162A JP 23332687 A JP23332687 A JP 23332687A JP 23332687 A JP23332687 A JP 23332687A JP S6476162 A JPS6476162 A JP S6476162A
Authority
JP
Japan
Prior art keywords
output
supplied
partial product
carrying
values
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP23332687A
Other languages
Japanese (ja)
Other versions
JP2629731B2 (en
Inventor
Takao Yamazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP23332687A priority Critical patent/JP2629731B2/en
Publication of JPS6476162A publication Critical patent/JPS6476162A/en
Application granted granted Critical
Publication of JP2629731B2 publication Critical patent/JP2629731B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

PURPOSE:To reduce a whole circuit scale and to improve an operation speed by supplying the adding output and the carrying output of a partial product and a third value to multiply a second value to a first value to a full adder and supplying these adding output and carrying output to a carry foreseeing adder. CONSTITUTION:Two values A and B to be multiplied are supplied to a partial product generating circuit 1, the generated partial product is supplied to a partial product adding circuit 2, and an adding output (s) and a carrying output (c) are obtained. These adding output (s) and carrying output (c) are supplied to full adders 3 and 4 respectively and are added to values C and E from a preceding step respectively. Further, the adding output (s) and the carrying output (c) from these full adders 3 and 4 are supplied to carry foreseeing adders (CLA) 5 and 6 respectively, and values D and F to be supplied to a succeeding step are obtained.
JP23332687A 1987-09-17 1987-09-17 Product-sum operation circuit Expired - Fee Related JP2629731B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23332687A JP2629731B2 (en) 1987-09-17 1987-09-17 Product-sum operation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23332687A JP2629731B2 (en) 1987-09-17 1987-09-17 Product-sum operation circuit

Publications (2)

Publication Number Publication Date
JPS6476162A true JPS6476162A (en) 1989-03-22
JP2629731B2 JP2629731B2 (en) 1997-07-16

Family

ID=16953388

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23332687A Expired - Fee Related JP2629731B2 (en) 1987-09-17 1987-09-17 Product-sum operation circuit

Country Status (1)

Country Link
JP (1) JP2629731B2 (en)

Also Published As

Publication number Publication date
JP2629731B2 (en) 1997-07-16

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees