JPS6450123A - Adding device - Google Patents
Adding deviceInfo
- Publication number
- JPS6450123A JPS6450123A JP20670987A JP20670987A JPS6450123A JP S6450123 A JPS6450123 A JP S6450123A JP 20670987 A JP20670987 A JP 20670987A JP 20670987 A JP20670987 A JP 20670987A JP S6450123 A JPS6450123 A JP S6450123A
- Authority
- JP
- Japan
- Prior art keywords
- carry
- adder
- delay time
- inputted
- bit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
PURPOSE:To execute a high speed calculation, and also, to decrease the number of elements by inputting simultaneously a block carry propagating signal and a block carry generating signal of a carry output by a first means and an output of a second means, to a third means. CONSTITUTION:When data Ai, Bi (i=0-31) are inputted to each adder 11, 12, 1 and 13, a carry C3 is outputted by a delay time of 3t (t is a delay time per one stage of a gate), in a 4-bit adder 11. Also, in 4-bit adders 12, 13 and a 5-bit adder 1, a block carry propagating signal Pi and a block carry generating signal Gi are generated. (i=0-3) Subsequently, the carry C3 is inputted to the adder 12, a carry C7 is outputted by a delay time of 1t, and the carry C7 and Pi, Gi are inputted to a 4-bit CLA 2. Next, carries C12, C17, C22 and C27 are inputted to the adder 1 and the adder 13 from the CLA 2 by a delay time of 1t, and the sum Si (i=13-31) and a carry output Cout are obtained by a delay time of 7t. In such a way, a high speed calculation can be executed, and also, the number of elements can be decreased.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20670987A JPS6450123A (en) | 1987-08-20 | 1987-08-20 | Adding device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20670987A JPS6450123A (en) | 1987-08-20 | 1987-08-20 | Adding device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6450123A true JPS6450123A (en) | 1989-02-27 |
Family
ID=16527814
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20670987A Pending JPS6450123A (en) | 1987-08-20 | 1987-08-20 | Adding device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6450123A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0590251A2 (en) * | 1992-09-22 | 1994-04-06 | Motorola, Inc. | High-speed adder |
| US5357457A (en) * | 1992-07-30 | 1994-10-18 | Mitsubishi Denki Kabushiki Kaisha | Adder with carry look ahead circuit |
| US5964827A (en) * | 1997-11-17 | 1999-10-12 | International Business Machines Corporation | High-speed binary adder |
-
1987
- 1987-08-20 JP JP20670987A patent/JPS6450123A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5357457A (en) * | 1992-07-30 | 1994-10-18 | Mitsubishi Denki Kabushiki Kaisha | Adder with carry look ahead circuit |
| EP0590251A2 (en) * | 1992-09-22 | 1994-04-06 | Motorola, Inc. | High-speed adder |
| EP0590251A3 (en) * | 1992-09-22 | 1994-08-31 | Motorola Inc | |
| US5375081A (en) * | 1992-09-22 | 1994-12-20 | Motorola, Inc. | High speed adder using a varied carry scheme and related method |
| US5964827A (en) * | 1997-11-17 | 1999-10-12 | International Business Machines Corporation | High-speed binary adder |
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