JPS56143051A - Data shift circuit - Google Patents
Data shift circuitInfo
- Publication number
- JPS56143051A JPS56143051A JP4549280A JP4549280A JPS56143051A JP S56143051 A JPS56143051 A JP S56143051A JP 4549280 A JP4549280 A JP 4549280A JP 4549280 A JP4549280 A JP 4549280A JP S56143051 A JPS56143051 A JP S56143051A
- Authority
- JP
- Japan
- Prior art keywords
- input
- gates
- data
- register
- bit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
- G06F7/527—Multiplying only in serial-parallel fashion, i.e. one operand being entered serially and the other in parallel
- G06F7/5272—Multiplying only in serial-parallel fashion, i.e. one operand being entered serially and the other in parallel with row wise addition of partial products
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
Abstract
PURPOSE:To obtain the multiplication circuit of high speed, by providing the gate between a plurality of data input terminals and the output terminals corresponding thereto, and picking up the signal at the input terminal different from the input terminal corresponding to the output terminal when the control signal is present. CONSTITUTION:In a multiplication circuit, the data in the multiplicand register 9 in 8-bits and in the multiplier register 10 are input to the adder 12 via the gate 11, and they are added to the output of the accumulator 13, and the addition output data S1-S8 are input to the correction gate 14. The data S1-S8 of the gate 14 are input to one end of the corresponding AND gates 17, 19...31. Further, the data S2-S8 are input to the AND gates 18, 20...32 with shift right by one bit. The gates 17...31 are closed by the inverter 16 with the multiplication instructions from the terminal 15, the gates 18...32 open and input is made to the accumulator 13 via the OR gates 33-40 with shift right by one bit. In this case, the register 10 is also shifted right by one bit. In this case, the register 10 is also shifted right by one bit, and this operation is repeated by the number of bits of the register 10 to obtain the specified result of multiplication.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4549280A JPS56143051A (en) | 1980-04-07 | 1980-04-07 | Data shift circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4549280A JPS56143051A (en) | 1980-04-07 | 1980-04-07 | Data shift circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS56143051A true JPS56143051A (en) | 1981-11-07 |
JPH0113129B2 JPH0113129B2 (en) | 1989-03-03 |
Family
ID=12720892
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4549280A Granted JPS56143051A (en) | 1980-04-07 | 1980-04-07 | Data shift circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56143051A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0278529A2 (en) * | 1987-02-13 | 1988-08-17 | Nec Corporation | Multiplication circuit capable of operating at a high speed with a small amount of hardware |
FR2645294A1 (en) * | 1989-04-04 | 1990-10-05 | Thomson Consumer Electronics | MULTIPLIER ASSEMBLY OF DIGITAL WORDS IN SERIES |
JPH04303233A (en) * | 1991-03-30 | 1992-10-27 | Toshiba Corp | Integrated circuit for display driving control and display system |
JP2008117218A (en) * | 2006-11-06 | 2008-05-22 | Mitsubishi Electric Corp | Arithmetic processor |
-
1980
- 1980-04-07 JP JP4549280A patent/JPS56143051A/en active Granted
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0278529A2 (en) * | 1987-02-13 | 1988-08-17 | Nec Corporation | Multiplication circuit capable of operating at a high speed with a small amount of hardware |
FR2645294A1 (en) * | 1989-04-04 | 1990-10-05 | Thomson Consumer Electronics | MULTIPLIER ASSEMBLY OF DIGITAL WORDS IN SERIES |
JPH04303233A (en) * | 1991-03-30 | 1992-10-27 | Toshiba Corp | Integrated circuit for display driving control and display system |
JP2008117218A (en) * | 2006-11-06 | 2008-05-22 | Mitsubishi Electric Corp | Arithmetic processor |
Also Published As
Publication number | Publication date |
---|---|
JPH0113129B2 (en) | 1989-03-03 |
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