JP2008117218A - Arithmetic processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an arithmetic processor allowing improvement of processing speed with a simple configuration without drastically increasing a circuit scale or a wiring resource, and capable of various kinds of arithmetic operations. <P>SOLUTION: In this arithmetic processor, an ALU 2 has: a first arithmetic part 3 having an AND circuit 7 performing AND processing of input data in each bit unit according to an arithmetic instruction and shift circuits 8a-8d performing shift processing to an AND operation result of each the bit unit by the desired number of bits; and an adder 4 executing addition processing with processing data by the shift circuits 8a-8d as addition input. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an arithmetic processing device that performs arithmetic processing on electronic data, and relates to an arithmetic processing device that performs data arithmetic processing in, for example, a digital still camera, a digital video camera, and an audio processing device.

  An arithmetic operation unit (Arithmetic Logic Unit; hereinafter referred to as ALU) that performs four arithmetic operations and logical operations, and a processor element (hereinafter referred to as PE) composed of a memory that temporarily stores the operation results from the ALU A SIMD (Single Instruction Multiple Data) device, which is an arithmetic processing device having a plurality of data, can process a large number of data with a single instruction. Thereby, it is used for high-speed processing, such as a moving image and a sound, for example.

  However, for example, with the increase in the number of pixels of a digital camera, there is a demand for higher speed by increasing the number of ALUs mounted on the SIMD apparatus. On the other hand, there is a demand for lower power consumption, that is, that further high-speed processing is possible with a small circuit scale.

  For example, in the conventional arithmetic processing device disclosed in Patent Document 1, a multiplier is provided to obtain a multiplication-dedicated or partial product in order to realize high-speed arithmetic for a multiplier having a large number of processing cycles.

JP 7-271555 A

  A conventional arithmetic processing unit has a multiplier dedicated to multiplication or a partial product for obtaining a partial product as a configuration in the multiplier, and there is a problem that the circuit scale increases although it is high speed.

  Furthermore, although the conventional arithmetic processing unit can perform an addition operation with a multiplier that is an arithmetic operation, it cannot perform a logical operation (AND or OR). Must be prepared.

  The present invention has been made to solve the above-described problems. The processing speed can be improved with a simple configuration without significantly increasing the circuit scale and wiring resources, and various kinds of arithmetic operations can be performed. An object of the present invention is to obtain an arithmetic processing device capable of

  An arithmetic processing apparatus according to the present invention includes an input memory that holds data to be calculated, a first calculation unit that executes a calculation according to a calculation command on the calculation target data read from the input memory, and a first calculation unit An arithmetic operation unit having a second operation unit that inputs operation result data and executes an operation according to the operation instruction, the arithmetic operation unit being operated by the first operation unit and the second operation unit according to the operation instruction By controlling the calculation, at least two types of calculations are executed.

  According to the present invention, the first arithmetic unit that performs an operation on the operation target data according to the operation instruction and the operation result according to the operation instruction by inputting the data of the operation result of the first operation unit. An arithmetic operation unit having two operation units, and the arithmetic operation unit executes at least two types of operations by controlling operations performed by the first operation unit and the second operation unit in accordance with the operation instructions. In addition, the processing speed can be improved with a simple configuration without greatly increasing the wiring resources, and various kinds of calculations can be performed.

Embodiment 1 FIG.
FIG. 1 is a diagram showing a configuration of an arithmetic processing apparatus according to the present invention. As shown in FIG. 1, the arithmetic processing apparatus according to the present invention includes an input memory 1, an ALU 2, and an output memory 5. The input memory 1 is a memory that stores data to be calculated. The ALU 2 that is an arithmetic operation unit includes a first operation unit 3 and a second operation unit 4.

  The output memory 5 is a memory that holds data processed by the ALU 2. In FIG. 1, a loop structure is formed in which the output of the output memory 5 is connected to the input of the input memory 1 so that the operation result data read from the output memory 5 can be fed back to the input memory 1.

  The first arithmetic unit 3 reads from the target data input memory 1 according to a desired arithmetic instruction (addition, subtraction, multiplication, logical sum, etc.) from a CPU (not shown), and performs a logical operation (logical sum, Invert, shift, etc.). The input memory 1 holds data to be calculated in advance.

  The second calculation unit 4 receives the data processed by the first calculation unit 3 and performs numerical calculation (addition or the like) according to the calculation command. As described above, according to the present invention, the calculation is performed separately into the logical operation that can execute the processing at high speed and the numerical operation that requires time.

  As a result, the processing time required for the numerical operation is dominant as the time required for the arithmetic processing, and the processing time required for the logical operation is almost negligible in comparison with this. Can be improved.

  FIG. 2 is a diagram showing the configuration of the ALU according to the first embodiment of the present invention. In the ALU, multiplication and addition can be switched and executed. As shown in FIG. 2, the first calculation unit 3 includes an AND circuit (AND) 7 and shift circuits (SHIFT) 8a to 8d. Both the AND circuit 7 and the shift circuits 8a to 8d are controlled to operate and stop by an arithmetic command from a CPU (not shown).

  The AND circuit (logical product circuit) 7 performs a logical product of the data A and B from the input memory 1 shown in FIG. The shift circuits 8 a to 8 d shift the calculation result of the AND circuit 7 by the set shift amount and output the result to the second calculation unit 4. In the example of FIG. 2, the second arithmetic unit 4 is configured by an adder (hereinafter referred to as adder 4 as appropriate). The adder 4 adds the outputs Pa to Pd from the shift circuits 8a to 8d, and outputs data Q as a calculation result.

Next, the operation will be described.
Thereafter, as shown in FIG. 3, binary notation is 1010 (decimal notation 10) as data A (4 bits), and binary notation is 0101 (decimal notation 5) as data B (4 bits). Calculated. 3A shows multiplication of data A and B, and FIG. 3B shows addition of data A and B.

(1) Multiplication Processing First, when the ALU 2 receives an arithmetic instruction indicating that multiplication processing is to be performed from a CPU (not shown), the internal AND circuit 7 receives the bit unit of each of the data A and data B input from the input memory 1. Calculate the logical product. For example, a bit obtained by performing a logical operation on the LSB (Least Significant Bit) bit value “1” (denoted as B [0] in FIG. 3A) of each bit of data A (1010) The value “1010” is output to the shift circuit 8d. For each bit of data A (1010), a bit value obtained by performing a logical operation on the value “0” of the second bit from the LSB of data B (indicated as B [1] in FIG. 3A) “0000” is output to the shift circuit 8c.

  For each bit of data A (1010), a bit value “1010” obtained by performing a logical operation on the value “1” of the third bit (indicated as B [2] in FIG. 3A) from the LSB of data B Is output to the shift circuit 8b. For each bit of data A (1010), a bit value “0000” obtained by logically operating the value “0” of the fourth bit (denoted as B [3] in FIG. 3A) from the LSB of data B Is output to the shift circuit 8a.

  The shift circuit 8a performs a right shift process (indicated as << 0 in FIG. 3A) on the logical operation result input from the AND circuit 7 by a shift amount “0”, and sets the process result as data Pa. Output to adder 4. The shift circuit 8b performs a shift amount “1”, that is, a 1-bit right shift process (indicated as << 1 in FIG. 3A) on the logical operation result input from the AND circuit 7, The result is output to the adder 4 as data Pb.

  Similarly, the shift circuit 8c performs a 2-bit right shift process (referred to as << 2 in FIG. 3A) on the logical operation result input from the AND circuit 7, and sets the process result as data Pc. Output to adder 4. The shift circuit 8d performs a 3-bit right shift process (represented as << 3 in FIG. 3A) on the logical operation result input from the AND circuit 7, and uses the process result as data Pd to adder 4 Output to.

  The adder 4 adds the shift result data Pa to Pd obtained from the first arithmetic unit 3 (Q = Pa + Pb + Pc + Pd). As a result, data Q (0110010) is obtained as a multiplication result of data A and data B.

(2) Addition processing First, when the ALU 2 receives an operation instruction to the effect that addition processing is to be performed from a CPU (not shown), the internal AND circuit 7 stops operating and the shift circuits 8a to 8d also do not perform shift processing. Data A and data B from the input memory 1 are output to the shift circuit 8a and the shift circuit 8d without being processed by the AND circuit 7, respectively. Further, 4-bit “0000” data is output to the shift circuits 8b and 8c, respectively.

  The shift circuit 8a performs a right shift process (indicated as << 0 in FIG. 3B) with a shift amount “0” on the input data A (1010), and the process result is used as data Pa. 4 is output. Further, the shift circuit 8b performs a right shift process with a shift amount “0” on the input data (0000), and outputs the processing result to the adder 4 as data Pb.

  Similarly, the shift circuit 8c performs a right shift process with a shift amount “0” on the input data (0000), and outputs the processing result to the adder 4 as data Pc. The shift circuit 8d performs a right shift process of the shift amount “0” on the input data B (0101), and outputs the processing result to the adder 4 as data Pd.

  The adder 4 adds the shift result data Pa to Pd obtained from the first arithmetic unit 3 (Q = Pa + Pb + Pc + Pd). As a result, data Q (01111) is obtained as the addition result of data A and data B.

  In the above description, the case where (1) multiplication processing and (2) addition processing are performed independently has been described. However, in many cases, the finally obtained operation ends with a single multiplication or addition. Is almost impossible and is done by many combinations of them. Therefore, in the present invention, as shown in FIG. 1, the value obtained as the calculation result of the ALU 2 is stored in the output memory 5 and fed back from the output memory 5 to the input memory 1 when used in a desired calculation. The above operation is repeated until a desired calculation result is obtained.

  As described above, according to the first embodiment, the AND circuit 7 that performs the logical product process on the input data in units of each bit according to the arithmetic instruction and the desired number of bits for the logical product operation result in each unit of bits. Since the ALU 2 includes the first arithmetic unit 3 having the shift circuits 8a to 8d for performing the shift processing and the adder 4 for executing the addition processing by using the processing data from the shift circuits 8a to 8d as an addition input, the same operation command is used. Since the configuration allows multiplication and addition, since at least a plurality of operations can be realized with the same configuration, a general-purpose and programmable arithmetic processing device can be obtained.

  In the first embodiment, since the calculation can be performed without providing a dedicated arithmetic circuit (for example, a multiplier) having a large circuit scale, the circuit scale can be reduced. Thus, power consumption can be reduced, and an arithmetic processing device suitable for arraying using a plurality of arithmetic processing devices can be configured.

  In the first embodiment, the data to be calculated is set to 4 bits, and the configuration for performing the calculation is shown. However, the present invention is not limited to this, and it corresponds to the processing bit of the data. Any configuration may be used.

Embodiment 2. FIG.
FIG. 4 is a diagram showing the configuration of the ALU of the arithmetic processing apparatus according to the third embodiment of the present invention. The overall configuration of the arithmetic processing apparatus is the same as that of FIG. 1 shown in the first embodiment. As shown in FIG. 4, the first calculation unit 3 according to the second embodiment includes a NOT circuit (NOT) 10 and a carry signal selection unit 11. Both the NOT circuit 10 and the carry signal selection unit 11 are controlled to operate and stop by a calculation command from a CPU (not shown).

  The NOT circuit (logic negation circuit) 10 performs inversion processing (logic negation) on the data A and B from the input memory 1 shown in FIG. 1 in accordance with a calculation instruction from a CPU (not shown). The carry signal selector 11 carries a carry signal Cin (carry from the lower digit) consisting of a bit value of 0 or 1 in accordance with an operation instruction from the CPU as a second operation unit (hereinafter referred to as adder 4 as appropriate). 4 is output.

  The adder 4 is constituted by a full adder, and inputs the data A and B processed by the NOT circuit 10 of the first arithmetic unit 3 as data Ain and Bin, and the carry signal Cin from the carry signal selection unit 11 To do. The multiplexer (selection processing unit) 12 selects either the data Q of the addition processing result by the adder 4 or the carry signal (data C) (carry to the upper digit) from the carry signal selection unit 11 and the operation result data Output as X.

Next, the operation will be described.
(1) Addition processing First, when the ALU 2 receives an arithmetic instruction to the effect of addition processing from a CPU (not shown), the internal NOT circuit 10 stops its operation. As a result, the data A and B input to the NOT circuit 10 are output to the adder 4 as data Ain and Bin as they are. At this time, the carry signal selection unit 11 outputs the bit value “0” as the carry signal to the adder 4 as the carry signal Cin (carry from the lower digit).

  The adder 4 adds the data Ain and the data Bin, and outputs the calculation result to the multiplexer 12 as data Q (A + B). On the other hand, the adder 4 outputs the carry signal Cin as it is to the multiplexer 12 as data C. In the multiplexer 12, the data input is switched to the operation output side of the adder 4 so as to select the output (data Q) of the operation result in the adder 4 in accordance with the operation instruction to the effect of addition processing from the CPU. .

  Thereby, data X (addition result of A + B) is obtained as an output from ALU2. If a carry signal (data C) (carry to the upper digit) is required, the input of data Q is selected by the multiplexer 12, and then the input of data C is selected to output data C as data X. That's fine.

(2) Subtraction processing When the ALU 2 receives an arithmetic instruction indicating that subtraction processing should be performed from a CPU (not shown), the internal NOT circuit 10 stops the inversion operation for the data A, while the inversion processing for the data B is performed. Execute. At this time, the carry signal selection unit 11 outputs “1” to the adder 4 as the carry signal Cin.

  For example, as in FIG. 3, when the data A is 4-bit 1010, the data Ain is 1010 as it is. When the data B is 4-bit 0101, the data Bin becomes 1010 by the inversion process.

  The adder 4 performs addition of the data Bin (data A), the data Bin (inversion of the data B), and the data B to which the carry signal Cin (1) is added as a two's complement. As a result, the calculation result of the adder 4 is output to the multiplexer 12 as data Q by subtraction (AB) of the data A and the data B. Also in this case, the adder 4 outputs the carry signal Cin as it is to the multiplexer 12 as data C.

  In the multiplexer 12, the data input is switched to the operation output side of the adder 4 so as to select the output (data Q) of the operation result in the adder 4 in accordance with the operation instruction to the effect of the subtraction processing from the CPU. . If data C, which is a carry to the upper digit, is required, the multiplexer 12 selects the input of data Q, then selects the input of data C (in this case, borrow) and outputs data C as data X. You can do it.

(3) Logical product processing The logical product (A & B) which is a logical operation follows the following formula which shows the carry generation logic of a full adder, as is well known.
C = (Ain & Bin) or (Bin & Cin) or (Ain & Cin)
Thereafter, the logical product of data A and data B is obtained using the above formula. That is, the data C is calculated from the above equation using the input data Ain, Bin, Cin of the adder 4.

  First, when the ALU 2 receives an arithmetic instruction indicating that a logical product is to be processed from a CPU (not shown), the internal NOT circuit 10 stops the inversion operation for the data A and the data B. At this time, carry signal selection unit 11 selects 4-bit data (0000) having a bit value “0” as carry signal Cin and outputs the selected data to adder 4. As a result, data A as data Ain, data B as data Bin, and “0” as the carry signal Cin are input to the adder 4.

  In the adder 4 which is a full adder, a logical product result of (Ain & Bin) is obtained as the carry output C to the upper digit from the above formula. In the multiplexer 12, the data input is switched to the carry output side of the adder 4 so that the carry output (data C) in the adder 4 is selected in accordance with an arithmetic instruction from the CPU indicating that logical product processing is to be performed. As a result, the logical product of the data A and B is obtained as the operation result of ALU2.

(4) Logical OR Processing First, when the ALU 2 receives an arithmetic instruction indicating that logical OR processing is to be performed from a CPU (not shown), the internal NOT circuit 10 stops the inversion operation for data A and data B. At this time, the carry signal selection unit 11 selects 4-bit data (1111) having a bit value “1” as the carry signal Cin and outputs it to the adder 4. As a result, the adder 4 receives data A as it is as data Ain, data B as it is as data Bin, and “1” as the carry signal Cin.

  In the adder 4 which is a full adder, a logical sum result of (Ain or Bin) is obtained as the carry output C to the upper digit from the above formula. In the multiplexer 12, the data input is switched to the carry output side of the adder 4 so as to select the carry output (data C) in the adder 4 in accordance with a calculation instruction from the CPU indicating that the logical sum processing is to be performed. Thereby, the logical sum of the data A and B is obtained as the operation result of the ALU2.

  As described above, according to the second embodiment, the NOT circuit 10 that performs the inversion processing of the input data according to the operation instruction and the carry signal selection unit 11 that selects the carry signal composed of any one of the 0 and 1 bit values are provided. An adder 4 composed of a full adder having the processing data from the NOT circuit 10 as an addition input and the selection data from the carry signal selection unit 11 as a carry from the lower digit, and an adder according to the operation instruction Since the ALU 2 is provided with the multiplexer 12 that selects the output data from 4 and outputs the result as the operation result, even the operation unit having the same configuration can execute at least two kinds of numerical operations or logical operations according to the operation instruction. As a result, the circuit scale can be further reduced.

  Moreover, in this Embodiment 2, since various calculations are possible, a more programmable arithmetic processing apparatus can be obtained. Further, in the second embodiment, addition and subtraction can be performed at substantially the same processing speed. Thus, by using the subtraction processing by the arithmetic processing apparatus of the second embodiment, it is possible to perform size comparison and condition separation at high speed without preparing a special comparator or the like.

Embodiment 3 FIG.
FIG. 5 is a diagram showing a configuration of an arithmetic processing apparatus according to Embodiment 3 of the present invention. As shown in FIG. 5, the arithmetic processing apparatus according to the third embodiment includes an input memory 15, ALUs 2-1, 2-2,..., Registers 16-1, 16-2,. 17, 17-2,..., Latches 18-1, 18-2,.

  The input memory 15 and the output memory 19 are memories that store unit data such as blocks or frames. Each of the ALUs 2-1 2-2,... Is connected to the registers 16-1, 16-2,..., And has the same configuration as that of the first embodiment or the second embodiment. Have. .. Hold the output data from each ALU 2-1, 2-2... As in the output memory 5 in the first embodiment.

  The header analysis units (determination processing units) 17-1, 17-2,... Analyze the header part of the instruction code in the arithmetic instruction shown in FIG. 6, and send the instruction code to the connected ALU. The latches (storage units) 18-1, 18-2,... Hold operation instructions from the operation instruction bus 20 to the corresponding ALU.

  In the arithmetic processing apparatus according to the third embodiment, at least two or more ALUs are serially connected from the input memory 15 to the output memory 19, and each ALU is connected by a single arithmetic instruction bus.

  FIG. 6 is a diagram showing the structure of an arithmetic instruction handled by the arithmetic processing unit in FIG. As shown in FIG. 6, the arithmetic instruction according to the third embodiment has a structure in which the processing order number is used as a header, and the arithmetic processing control code is an instruction code (control code for the arithmetic unit of each ALU).

Next, the operation will be described.
The data stored in the input memory 15 is output to the ALU 2-1 for performing a desired calculation. The ALU 2-1 operates in the same manner as in the first embodiment and the second embodiment. At this time, when an arithmetic instruction is sent from the CPU (not shown) to each ALU connected in serial via the arithmetic instruction bus 20, the arithmetic instruction is held in the latch 18-1.

  The header analysis unit 17-1 analyzes the header of the arithmetic instruction held in the latch 18-1, decodes the processing order number, and outputs the processing order number to the ALU 2-1. For example, in the case of an arithmetic instruction for the ALU 2-1 having the first arrangement order, “1” is described as the processing order number in the header.

  As described above, the instruction code once held in the latch 18-1 is obtained when the processing order number decoded (or compared) by the header analysis unit 17-1 matches the processing order of the corresponding ALU. Only to the ALU 2-1. The header analysis units 17-1, 17-2,... Are numbered in advance in the order of processing. Upon receiving the instruction code, the ALU 2-1 performs arithmetic processing on the input data according to the instruction code, and outputs the arithmetic result to the register 16-1.

  Similarly, when “2” is attached to the header of the operation instruction as the processing order, the header analysis unit 17-2 sends the instruction code in the operation instruction to the ALU 2-2. As a result, the ALU 2-2 performs an operation on the input data according to the instruction code. During this time, an instruction code with processing order “1” attached to the ALU 2-1 is sent as an operation instruction, and the ALU 2-1 performs an operation on another data stored in the input memory 15.

  Thus, after performing a desired calculation, the final calculation result is stored in the output memory 19.

  As described above, according to the third embodiment, at least two or more ALUs are serially connected, the processing order is attached to the instruction code, and the instruction code corresponding to the processing order is output to the corresponding ALU. For example, audio stream data and image raster data such as a CCD sensor can be processed in real time.

  In addition, since the arithmetic instruction bus 20 for giving arithmetic instructions to each ALU is composed of a single (common bus), it is possible to reduce the wiring load on the bus and to obtain an arithmetic processing device with a small circuit scale. .

  In the third embodiment, an example in which one ALU performs one operation is shown. However, when there are a large number of desired operation steps, the number of ALUs must be provided. Therefore, if the number of ALUs is M and the number of operation steps is N, when M <N, a plurality of operation steps are sent to the ALU 2-1 using the feedback path from the register 16-1 to the ALU 2-1 shown in FIG. By performing this calculation, a desired calculation result can be obtained.

  In this case, the number of operation steps for each ALU 2-1, 2-2,... Is determined in advance. An arithmetic instruction with a corresponding header “1” may be used.

  In the third embodiment, the header contents of the arithmetic instruction are used as a latch that holds the arithmetic instruction and a header analysis unit that outputs the instruction code of the arithmetic instruction held by the latch according to the analysis result of the arithmetic instruction to the ALU. Although an example using a decoder for decoding or a comparator for comparing the processing order set in itself with the header contents has been shown, other means may be used as long as this function can be achieved.

It is a figure which shows the structure of the arithmetic processing apparatus by this invention. It is a figure which shows the structure of ALU by Embodiment 1 of this invention. FIG. 6 is a diagram for explaining ALU arithmetic processing according to the first embodiment; It is a figure which shows the structure of ALU by Embodiment 2 of this invention. It is a figure which shows the structure of the arithmetic processing apparatus by Embodiment 3 of this invention. It is a figure which shows the structure of the arithmetic instruction handled with the arithmetic processing unit in FIG.

Explanation of symbols

  1,15 input memory, 2,2-1,2-2... ALU, 3 first operation unit, 4 second operation unit (adder), 5,19 output memory, 7 AND circuit (logical product circuit) , 8a to 8d shift circuit, 10 NOT circuit (logic negation circuit), 11 carry signal selection unit, 12 multiplexer (selection processing unit), 16-1, 16-2... Register, 17-1, 17-2. .. Header analysis unit (determination processing unit), 18-1, 18-2... Latch (storage unit), 20 arithmetic instruction bus.

Claims (7)

An input memory that holds data to be calculated;
A first operation unit that executes an operation according to an operation instruction on the operation target data read from the input memory, and an operation result according to the operation instruction by inputting data of an operation result by the first operation unit An arithmetic operation unit having a second operation unit,
The arithmetic processing unit is an arithmetic processing unit that executes at least two types of arithmetic operations by controlling arithmetic operations by the first arithmetic unit and the second arithmetic unit in accordance with the arithmetic instructions. The first operation unit performs a logical operation according to the operation instruction,
The arithmetic processing apparatus according to claim 1, wherein the second arithmetic unit performs a numerical operation according to an arithmetic instruction. A first arithmetic unit that performs a logical product operation on a bit-by-bit basis on the operation target data read from the input memory; inputs a logical product operation result of each bit unit from the logical product circuit; A shift circuit that performs shift processing in bit units,
The second arithmetic unit is composed of an adder for adding data from the shift circuit,
The arithmetic operation unit performs addition processing and multiplication processing on the operation target data read from the input memory by controlling the logical product operation by the logical product circuit and the shift processing by the shift circuit in accordance with the arithmetic instruction. The arithmetic processing apparatus according to claim 1, wherein the arithmetic processing apparatus is characterized. The arithmetic unit is
The first arithmetic unit includes a logical negation circuit that performs a logical negation operation on the operation target data read from the input memory, and a carry signal selection unit that selects a carry signal composed of either 0 or 1 bit value. Have
The second arithmetic unit is composed of a full adder that inputs the data from the logical negation circuit and the carry signal selected by the carry signal selection unit, and outputs these addition processing results or carry signals,
A selection processing unit that selects an addition processing result or a carry signal by the second arithmetic unit according to an arithmetic instruction and outputs the result as an arithmetic result,
By performing a logical negation operation by the logical negation circuit and a carry signal selection by the carry signal selection unit according to an operation instruction, a numerical operation process and a logical operation process are performed on the operation target data read from the input memory. The arithmetic processing apparatus according to claim 1, wherein: Equipped with an output memory that holds the data of the results of arithmetic operations.
5. The arithmetic processing device according to claim 1, wherein data held in the output memory is fed back to the input memory as operation target data in accordance with an arithmetic instruction. 6. An input memory that holds data to be calculated;
An arithmetic operation unit group formed by connecting at least two arithmetic operation units according to any one of claims 1 to 4 in series;
A register which is provided between the arithmetic operation units connected in series in the arithmetic operation unit group, holds an operation result by the preceding arithmetic operation unit, and outputs the held data as operation target data of the subsequent arithmetic operation unit;
A storage unit that is provided for each arithmetic operation unit, and stores operation instructions attached with the connection order of the arithmetic operation units;
A determination processing unit that determines the connection order of the arithmetic operation units from the operation instructions held in the storage unit, and outputs an instruction code in the operation instructions to the arithmetic operation unit corresponding to the connection order according to the determination result; Prepared,
Each arithmetic operation unit of the arithmetic operation unit group is an arithmetic processing unit that executes at least two types of operations by controlling operations performed by the first operation unit and the second operation unit in accordance with an instruction code in the operation instruction.   7. The arithmetic processing apparatus according to claim 6, wherein the data of the operation result held in the register in accordance with the operation instruction is fed back as operation target data by the preceding arithmetic operation unit.

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