JP2012059131A - Simd microprocessor and processing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve throughput of an entire system by quickly generating a histogram of gray scale values.SOLUTION: Each of processor elements PEn (n=0 to 255) has n addresses corresponding to n gray scale values. A micro-counter 12 has a bit width shorter than a bit width of a counter register 15. Each time an address signal including a pixel value of pixel data as an address is input from an external data transfer device 2, the micro-counter 12 of a processor element PEn having the address included in the input address signal increments a count value C12 by one. A global processor 10 executes, at prescribed timing, parallel addition processing of controlling an ALU (Arithmetic Logic Unit) 14 so that the count value C12 is accumulated to a count value C15 stored in the corresponding counter register 15, and the global processor 10 performs such control as to reset the count value C12 stored in each micro-counter 12.

Description

  The present invention relates to a single instruction stream multiple data stream (SIMD) type microprocessor that processes a plurality of data in parallel by one arithmetic instruction and a processing method of the SIMD type microprocessor.

  A microprocessor dedicated to image processing often employs a SIMD type microprocessor (see, for example, Patent Document 1). This is because the feature of the SIMD microprocessor that the same arithmetic processing can be executed simultaneously on a plurality of data with one instruction is suitable for image processing. The SIMD type microprocessor is configured to include a plurality of processor elements (hereinafter referred to as PE (Processor Element)) each including an arithmetic unit and a register, and by performing control so that arithmetic processing is simultaneously performed in the plurality of PEs. , Increase the efficiency of image processing. Since each PE is in charge of image processing of data corresponding to one pixel, it is possible to simultaneously perform arithmetic processing on data corresponding to a plurality of pixels.

  However, among the processes that handle image data, there are processes that cannot obtain the parallel operation effect by the SIMD type microprocessor. For example, the process of obtaining the median (median value) of the gradation values of the image data is required in the median filter process and the image process described in Patent Document 2, but cannot be realized by the parallel operation. Specifically, as a procedure for obtaining the median, after rearranging the gradation value of each pixel in the descending order or ascending order, the gradation value having a rank corresponding to one-half of the parameter is obtained. Alternatively, there is a method of adopting a gradation value when the cumulative frequency reaches one-half of the parameter after creating the histogram. However, since the former performs rearrangement processing, it cannot obtain a parallel operation effect, and the latter cannot obtain a parallel operation effect when creating a histogram. Therefore, a SIMD microprocessor for image processing is required to have a technique for creating a histogram at high speed.

  In Patent Document 1, a unique address is assigned to each PE, and image data is transmitted and received between an external device of a SIMD type microprocessor such as an external data transfer device and an arbitrary PE by designating the address. A method is disclosed. With reference to FIG. 9, a histogram generation process according to the related art for generating a histogram of gradation values of 256-gradation pixel data using the method described in Patent Document 1 will be described.

  FIG. 9 is a block diagram showing a configuration of a SIMD type microprocessor 1P according to the prior art. 9, the SIMD type microprocessor 1P includes a global processor (hereinafter referred to as GP (Global Processor)) 10 and 256 processor elements PE0P, PE1P,..., PE255P. Here, the GP 10 is an SISD (Single Instruction Stream, Single Data Stream) type processor, and controls the overall operation of the SIMD type microprocessor 1P and each operation of the processor elements PE0P to PE255P, and an external data transfer device. 2 transmits operation setting data, a command for data transfer, and the like. Each processor element PEnP (n = 0, 1,..., 255) includes a decoder and controller 11, a port register 40, an arithmetic logic operation circuit (hereinafter referred to as ALU (Arithmetic Logic Unit)) 14, and a counter register. 15 and the cumulative operation circuit 13 and the operation data buses 21 and 22. Each processor element PEnP is assigned a unique address n corresponding to the processor element number n.

  In FIG. 9, the external data transfer device 2 is connected to the processor elements PE0P to PE255P, and receives a control signal for instructing reading or writing of data and a unique address of the processor element of the reading source or writing destination. The address signal shown is generated and output to the processor elements PE0P to PE255P. In each processor element PEnP, the decoder and controller 11 determines that the address included in the input address signal matches the address n assigned to the processor element PEnP and the input control signal indicates data reading. An instruction signal S11 for instructing data reading is output to the port register 40, and in response to this, the port register 40 outputs the data stored in the port register 40 to the external data transfer device 2 via the data bus. . In each processor element PEnP, the decoder and controller 11 determines that the address included in the input address signal matches the address n assigned to the processor element PEnP and the input control signal indicates data writing. In addition, an instruction signal S11 for instructing data writing is output to the port register 40, and in response to this, the data output from the external data transfer device 2 to the data bus is stored in the port register 40. As described above, data transfer is performed between the data transfer device 2 and each processor element PEnP.

  Further, in FIG. 9, the GP 10 performs arithmetic processing on the data stored in each port register 40 using an arithmetic circuit such as the cumulative arithmetic circuit 13. Here, since the external data transfer device 2 and the GP 10 operate independently of each other, the external data transfer device 2 reads out the data in each port register 40 while performing the arithmetic processing by the GP 10, and others. Can be transferred to the external device, or data from other external devices can be written to each port register 40. For this reason, the GP 10 does not spend an instruction step for data transfer processing with an external device.

  The external data transfer device 2 in FIG. 9 normally accesses each processor element PEnP in the order according to the processor element number n using an address counter or the like. At this time, by associating each address n with the gradation value n of the pixel data, the SIMD microprocessor 1P can be used to generate a gradation value histogram, as will be described below.

  First, the GP 10 resets all the counter registers 15. After that, the external data transfer device 2 sends an address signal including the gradation value of the input pixel data (a value between 0 and 255) as an address and a control signal indicating data writing to each decoder and The data is output to the controller 11 (hereinafter referred to as data transfer processing). In response to this, the decoder and controller 11 of the processor element PEnP to be written writes the data value “1” to the corresponding port register 40, and the decoder and controller 11 other than the processor element PEnP to be written receive the corresponding port. A data value “0” is written to the register 40. Further, each port register 40 outputs the stored data C40 to the ALU 14 via the arithmetic data bus 21, and each counter register 15 outputs the stored data C15 to the ALU 15 via the arithmetic data bus 22. Next, the GP 10 controls all the ALUs 14 to add the input data C40 and the data C15 and store the addition result data C15 in the counter register 15 (hereinafter referred to as parallel addition processing). . By alternately and repeatedly executing the data transfer process by the external data transfer apparatus 2 and the parallel addition process by the GP 10 described above, the counter register 15 of each processor element PE0P, PE1P,. , 1,..., 255 are stored.

  However, in the histogram generation processing according to the prior art, it is necessary to execute parallel addition processing by GP10 every time the data transfer processing by the external data transfer device 2 is executed once, and a relatively long time is required for generation of the histogram. And In addition, during the histogram generation process, the SIMD type microprocessor 1P is used exclusively for the histogram generation process, and other processes cannot be executed at the same time, resulting in a problem that the throughput of the entire system is reduced.

  An object of the present invention is to solve the above problems, and to provide a SIMD type microprocessor capable of generating a histogram at a higher speed than the prior art and improving the throughput of the entire system, and a processing method therefor.

The SIMD type microprocessor according to the first invention is:
In a SIMD type microprocessor that sequentially inputs an address signal including pixel values of pixel data as addresses and generates a histogram of each pixel value of a plurality of pixel data,
A plurality of processor elements each having a unique address corresponding to a pixel value, and a storage unit having a predetermined first bit width and storing a frequency of the pixel value corresponding to the unique address A plurality of processor elements each having an adding means and a counter means having a predetermined second bit width smaller than the first bit width and storing a predetermined count value;
Control means for controlling each of the processor elements,
Each time the address signal is input to the SIMD type microprocessor, the counter means of the processor element having the address included in the input address signal increments the count value by 1.
The control means sets the cumulative addition means so as to cumulatively add the count value stored in the counter means of each processor element to the frequency stored in the storage means corresponding to the counter means at a predetermined timing. The parallel addition process to be controlled is executed, and the count value stored in the counter means of each processor element is controlled to be reset.

In the SIMD type microprocessor, the count value stored in at least one of the counter means of the plurality of processor elements becomes a predetermined threshold count value corresponding to the second bit width. And further comprising an interrupt request signal generating means for generating an interrupt request signal and outputting it to the control means,
In response to the interrupt request signal, the control means performs the parallel addition process and controls the count value stored in the counter means of each processor element to be reset to zero. .

  In the SIMD type microprocessor, the counter means of each processor element is a shift register including a plurality of cascade-connected registers.

Further, in the SIMD type microprocessor, each processor element further includes an encoder that encodes a count value stored in the shift register into binary data and outputs the binary data to the cumulative addition unit corresponding to the shift register,
The cumulative addition means of each processor element is characterized in that instead of the count value, binary data input from the encoder corresponding to the cumulative addition means is cumulatively added to the frequency stored in the storage means. To do.

  Still further, in the SIMD type microprocessor, the cumulative addition means of each processor element includes an arithmetic logic operation circuit for the cumulative addition.

  In the SIMD type microprocessor, the pixel value is a gradation value.

The processing method of the SIMD type microprocessor according to the second invention is as follows:
In a processing method of a SIMD type microprocessor that sequentially inputs an address signal including a pixel value of pixel data as an address and generates a histogram of each pixel value of a plurality of pixel data,
The SIMD type microprocessor is
A plurality of processor elements each having a unique address corresponding to a pixel value, and a storage unit having a predetermined first bit width and storing a frequency of the pixel value corresponding to the unique address A plurality of processor elements each having an adding means and a counter means having a predetermined second bit width smaller than the first bit width and storing a predetermined count value;
Control means for controlling each of the processor elements,
The above processing method is
Each time the address signal is input to the SIMD type microprocessor, a counter means of a processor element having an address included in the input address signal increments the count value by one;
Each of the cumulative addition means is configured to cumulatively add the count value stored in the counter means of each processor element to the frequency stored in the storage means corresponding to the counter means at a predetermined timing. Performing parallel addition processing to be controlled, and controlling to reset the count value stored in the counter means of each processor element.

In the processing method of the SIMD type microprocessor, the SIMD type microprocessor has a count value stored in at least one of the counter means of the plurality of processor elements corresponding to the second bit width. An interrupt request signal generating means for generating an interrupt request signal and outputting it to the control means when a predetermined threshold count value is reached;
In the processing method, in response to the interrupt request signal, the control unit performs the parallel addition processing and controls the count value stored in the counter unit of each processor element to be reset to zero. The method further includes a step.

  Further, in the processing method of the SIMD type microprocessor, the counter means of each processor element is a shift register including a plurality of cascade-connected registers.

Furthermore, in the processing method of the SIMD type microprocessor, each processor element encodes a count value stored in the shift register into binary data, and outputs an encoder to the cumulative addition means corresponding to the shift register. In addition,
In the processing method, the cumulative addition means of each processor element cumulatively adds binary data input from the encoder corresponding to the cumulative addition means to the frequency stored in the storage means instead of the count value. The method further includes the step of:

  Still further, in the processing method of the SIMD type microprocessor, the cumulative addition means of each processor element includes an arithmetic logic circuit for the cumulative addition.

  In the processing method of the SIMD type microprocessor, the pixel value is a gradation value.

  According to the SIMD type microprocessor and the processing method of the SIMD type microprocessor according to the present invention, each processor element of the SIMD type microprocessor has a unique address corresponding to the pixel value, and has a predetermined first bit width. A cumulative addition means having storage means for storing the frequency of the pixel value corresponding to the unique address, a predetermined second bit width smaller than the first bit width, and a predetermined count value Counter means for storing. Each time an address signal is input to the SIMD type microprocessor, the counter means of the processor element having the address included in the input address signal increments the count value by one. Further, the control means adds each of the cumulative addition means so as to cumulatively add the count value stored in the counter means of each processor element to the frequency stored in the storage means corresponding to the counter means at a predetermined timing. The parallel addition processing to be controlled is executed, and the count value stored in the counter means of each processor element is controlled to be reset. Therefore, a histogram can be generated at a higher speed than in the prior art, and the throughput of the entire system can be improved.

1 is a block diagram showing a configuration of a SIMD type microprocessor 1 according to a first embodiment of the present invention. It is a sequence diagram which shows the histogram generation process performed by the SIMD type | mold microprocessor 1 of FIG. It is a block diagram which shows the structure of the SIMD type microprocessor 1A which concerns on the 2nd Embodiment of this invention. FIG. 4 is a sequence diagram showing a histogram generation process executed by the SIMD type microprocessor 1 </ b> A of FIG. 3. It is a block diagram which shows the structure of the SIMD type | mold microprocessor 1B which concerns on the 3rd Embodiment of this invention. FIG. 6 is a sequence diagram showing a histogram generation process executed by the SIMD type microprocessor 1 </ b> B of FIG. 5. It is a block diagram which shows the structure of SIMD type microprocessor 1C which concerns on the 4th Embodiment of this invention. FIG. 8 is a sequence diagram showing a histogram generation process executed by the SIMD type microprocessor 1 </ b> C of FIG. 7. It is a block diagram which shows the structure of the SIMD type microprocessor 1P which concerns on a prior art.

  Hereinafter, embodiments according to the present invention will be described with reference to the drawings. In addition, in each following embodiment, the same code | symbol is attached | subjected about the same component.

First embodiment.
FIG. 1 is a block diagram showing a configuration of a SIMD type microprocessor 1 according to the first embodiment of the present invention, and FIG. 2 is a sequence showing a histogram generation process executed by the SIMD type microprocessor 1 of FIG. FIG. In FIG. 1, the same data bus as that in FIG. 9 is illustrated, but is not used in the histogram generation processing according to the following embodiments. In FIG. 1, the SIMD type microprocessor 1 is used to generate a histogram of gradation values of 256 gradation pixel data input to the external data transfer device 2. The SIMD type microprocessor 1 includes a GP 10 and 256 processor elements PE0, PE1,..., PE255. Here, the GP 10 is a SISD type processor, controls the entire operation of the SIMD type microprocessor 1 and each operation of the processor elements PE0 to PE255, and sets operation data for the external data transfer device 2. Send commands for data transfer. Further, each processor element PEn (n = 0, 1,..., 255) includes a decoder and controller 11, a microcounter (small frequency counter) 12, an ALU 14 and a cumulative adder circuit 13 including a counter register 15, and an arithmetic operation. The data buses 21 and 22 are provided. Here, each processor element PEn is assigned a unique address n corresponding to the processor element number n.

  In FIG. 1, the external data transfer device 2 operates in synchronization with the SIMD type microprocessor 1. Each time the external data transfer device 2 inputs pixel data from an external device such as a memory, the external data transfer device 2 generates an address signal including the gradation value of the input pixel data as an address and a control signal indicating data writing, The data is output to the decoder and controller 11 of each processor element PEn. In each processor element PEn, the decoder and controller 11 instructs to count up when the address included in the input address signal matches the address n of the processor element PEn and the control signal indicates data writing. A signal S11 is generated and output to the microcounter 12. The microcounter 12 resets the count value C12 to zero in response to the reset command from the GP 10, and increments the count value C12 by 1 in response to the instruction signal S11 indicating data writing. The output terminal of the microcounter 12 is connected to one input terminal of the ALU 14 via the arithmetic data bus 21.

  Further, in FIG. 1, the counter register 15 stores the count value C14 from the ALU 14 as the count value C15, and resets the count value C15 to zero in response to a reset command from the GP 10. The output terminal of the counter register 15 is connected to the other input terminal of the ALU 14 via the arithmetic data bus 22. The ALU 14 adds the input count value C12 and the count value C15 in response to the cumulative addition instruction A0 from the GP 10, and outputs the count value C14 of the addition result to the counter register 15.

  Here, in FIG. 1, the counter register 15 is a register that is also used for calculation in the SIMD type microprocessor 1 </ b> P according to the related art, and is not a component provided exclusively for histogram generation processing described later with reference to FIG. 2. . The counter register 15 has a bit width capable of storing data processed in each processor element PEn. The bit width of the micro counter 12 is smaller than the bit widths of the counter register 15 and the ALU 14. For example, the bit width of the counter register 15 and the ALU 14 is 16 bits, and the bit width of the micro counter 12 is 8 bits.

  Next, a histogram generation process executed by the SIMD type microprocessor 1 will be described with reference to FIG. First, the GP 10 outputs a reset command to the micro counter 12 and the counter register 15 of each processor element PEn. In response to this, in each processor element PEn, the micro counter 12 resets the count value C12 to zero, and the counter register 15 resets the count value C15 to zero. Next, the GP 10 outputs to the external data transfer apparatus 2 a process start command that instructs to start process A1 described later. In response to this, the external data transfer device 2 executes the process A1.

  In the process A1, when the external data transfer device 2 inputs one pixel data from the external device, the external data transfer device 2 generates an address signal including the gradation value of the input pixel data as an address and a control signal indicating data writing. To the decoder and controller 11 of each processor element PEn. In response to this, the decoder and controller 11 of each processor element PEn determines whether the address included in the input address signal is n and whether the input control signal indicates data writing, and YES In the case of, the instruction signal S11 instructing the count up is generated and outputted to the microcounter 12, while in the case of NO, the instruction signal S11 is not generated. Further, in response to the instruction signal S11 instructing the count up, the microcounter 12 increments the count value C12 by one.

  The data transfer device 2 repeats the process A1 described above as many times as the maximum value of the count value C12 that can be counted by the microcounter 12. Specifically, in the present embodiment, the maximum value of the count value C12 is 255, and the process A1 is repeatedly executed only 255 times. Thus, the count value C12 corresponding to the number of pixel data having the gradation value n among the input pixel data is stored in the microcounter 12 of the processor element PEn having the address n corresponding to each gradation value n. The However, since the count value C12 can only express a value between 0 and 255, when the process A1 is repeated 256 times or more, only pixel data having a specific gradation value is input to the external data transfer device 2. In such a case, the micro counter 12 of the processor element having an address corresponding to the gradation value causes an overflow. For this reason, after the process A1 is repeatedly executed 255 times, a parallel addition process PA described below is executed.

  In the parallel addition process PA of FIG. 2, the GP 10 outputs the cumulative addition instruction A0 to the ALUs 14 of all the processor elements PE0 to PE255. In response to this, the ALU 14 of each processor element PEn adds the count value C12 and the count value C15, and outputs the count value C14 of the addition result to the counter register 15. Since the addition processing by the ALUs 14 of the processor elements PE0 to PE255 is executed by the parallel operation function of the SIMD type microprocessor 1, it ends in a relatively short time. After the parallel addition process PA, the GP 10 outputs a reset instruction to the micro counter 12 of each processor element PEn. In response to this, the count values C12 of all the microcounters 12 are reset to zero.

  In FIG. 2, a process B1 including a process A1 of 255 times, a parallel addition process PA, and a subsequent reset process of the microcounter 12 is repeatedly executed until the process for the last pixel data is completed. As a result, the count value C15 corresponding to the frequency of the gradation value n is stored in the counter register 15 of each processor element PEn. Thereafter, the external data transfer device 2 outputs a process end notification indicating that the last pixel data has been processed to the GP 10. In response to this, the GP 10 outputs a read command to the counter register 15 of each processor element PEn, and in response to this, each counter register 15 outputs the count value C15 to the GP 10 for histogram generation processing. Exit.

  As described above, in the SIMD type microprocessor 1 according to the present embodiment, each processor element PEn has a unique address n corresponding to the gradation value n. Each processor element PEn has a bit width of 16 bits and includes a cumulative addition circuit 13 including a counter register 15 that stores a count value C15 corresponding to the frequency of the gradation value n corresponding to the address n, and 8 And a microcounter 12 having a bit width of bits and storing a count value C12. Each time an address signal is input to the SIMD type microprocessor 1 from the external data transfer device 2, the microcounter 12 of the processor element PEn having the address n included in the input address signal sets the count value C12 to 1. Increment only. Furthermore, the global processor 10 repeats the process A1 of FIG. 2 only 255 times and stores the count value C12 stored in the microcounter 12 of each processor element PEn in the counter register 15 corresponding to the microcounter 12. A parallel addition process PA for controlling each cumulative addition circuit 13 to perform cumulative addition to the stored count value C15 is executed, and control is performed to reset the count value C12 stored in the microcounter 12 of each processor element PEn. To do.

  Therefore, according to the present embodiment, since the micro counter 12 is provided in each processor element PEn, it is not necessary to execute the cumulative addition instruction A0 for each pixel data to be processed, and the histogram can be made faster than in the conventional technique. Can be generated. Further, since the SIMD type microprocessor 1 can execute other processes during the period in which the process A1 of FIG. 2 is executed a number of times equal to the maximum value of the count value C12 stored in the microcounter 12, In comparison, the overall system throughput is improved. Further, the SIMD type microprocessor 1 can be realized only by further providing a microcounter 12 as compared with the SIMD type microprocessor 1P (see FIG. 9) according to the prior art. Generally, in the SIMD type microprocessor 1P according to the prior art, the bit width of the port register 40 is equal to the bit width of the cumulative addition circuit 13 (for example, 16 bits), but the SIMD type microprocessor 1 according to the present embodiment. The bit width (in this embodiment, 8 bits) of the microcounter 12 provided in is smaller than the bit width of the port register 40. For this reason, the size of the component newly added to the SIMD type microprocessor 1P according to the prior art can be relatively small.

  In the present embodiment, the process A1 is repeatedly executed only 255 times. However, the present invention is not limited to this, and the process A1 may be repeatedly executed the number of times equal to or less than the maximum value of the count value C12.

  Further, after reading the count value C15 from each counter register 15, the pixel data to be processed may be added, and the process B1 may be continued.

  Further, although the bit width of the microcounter 12 is 8 bits, the present invention is not limited to this, and it may be smaller than the bit width of the counter register 15.

Second embodiment.
FIG. 3 is a block diagram showing a configuration of a SIMD type microprocessor 1A according to the second embodiment of the present invention, and FIG. 4 is a sequence showing a histogram generation process executed by the SIMD type microprocessor 1A of FIG. FIG.

  In FIG. 3, a SIMD type microprocessor 1A outputs GP10, 256 processor elements PE0A, PE1A,..., PE255A, an IRQ (Interrupt ReQuest) signal line 31 connected to GP10, and a predetermined power supply voltage Vcc. And a pull-up resistor 32 connected between the direct current power source and the IRQ signal line 31. Each processor element PEnA is assigned a unique address n corresponding to the processor element number n. Here, each processor element PEnA further includes an IRQ condition determination circuit 16 and an N-channel MOS field effect transistor (hereinafter referred to as nMOSFET) 17 as compared with the processor element PEn according to the first embodiment. It is characterized by being configured.

  In each processor element PEnA, the nMOSFET 17 has a gate connected to the IRQ condition determination circuit 16, a drain connected to the IRQ signal line 31, and a grounded source. That is, all the nMOSFETs 17 are wired or connected to each other. In each processor element PEnA, the IRQ condition determination circuit 16 detects the count value C12 of the microcounter 12, and the detected count value C12 is the maximum value of the count value C12 (in this embodiment, 255). Is controlled to turn on the nMOSFET 17. With the above configuration, when at least one nMOSFET 17 is turned on, the voltage level of the IRQ signal line 31 is set to a low level. Hereinafter, when the voltage level of the IRQ signal line 31 is set to the low level, the interrupt request signal is generated. Each IRQ condition determination circuit 16 and nMOSFET 17 of the processor elements PE0A to PE255A, the IRQ signal line 31, and the pull-up resistor 32 are stored in at least one of the microcounters 12 of the processor elements PE0A to PE255A. When the count value C12 reaches a predetermined threshold count value (255 in this embodiment) corresponding to the bit width of the microcounter 12, an interrupt request signal is generated and output to the GP10. An interrupt request signal generating means is configured. In response to the interrupt request signal, the GP 10 executes a parallel addition process PA.

  Next, a histogram generation process executed by the SIMD type microprocessor 1A will be described with reference to FIG. First, the GP 10 outputs a reset command to the micro counter 12 and the counter register 15 of each processor element PEn. In response to this, in each processor element PEnA, the micro counter 12 resets the count value C12 to zero, and the counter register 15 resets the count value C15 to zero. Next, the GP 10 outputs to the external data transfer device 2 a process start command that instructs to start the process A1 similar to the process A1 of FIG. In response to this, the external data transfer device 2 executes the process A1. In the present embodiment, every time the process A1 is executed, the IRQ condition determination circuit 16 of each processor element PEn determines whether or not the input count value C12 is 255, and when it is NO, the corresponding nMOSFET 17 Control to turn on. As a result, an interrupt request signal is generated and output to the GP 10 as described above. That is, an interrupt request signal is generated when the count value C12 is 255 in at least one processor element PEnA. When the count value C12 is less than 255 in all the processor elements PE0A to PE255A, the process A2 including the process A1 and the determination process by the IRQ condition determination circuit 16 is repeatedly executed as shown in FIG. The That is, when the process A2 is executed, the count value C12 of any one of the microcounters 12 is incremented by 1. When the process A2 is repeatedly executed, the count value C12 of each microcounter 12 increases, and when the count value C12 of at least one microcounter 12 becomes 255, the corresponding IRQ condition determination circuit 16 generates an interrupt request signal. Is output to the GP 10.

  In response to the interrupt request signal, the GP 10 controls the external data transfer device 2 so as not to execute the process A2, executes the parallel addition process PA similar to FIG. 2 as the interrupt process, and sends a reset instruction to each processor. Output to the micro counter 12 of the element PEn. In response to this, the count values C12 of all the microcounters 12 are reset to zero. Further, the GP 10 controls the external data transfer device 2 so as to execute the process A2. In FIG. 4, a process B2 including a process A2, a parallel addition process PA, and a subsequent reset process of the microcounter 12 is repeatedly executed until the process for the last pixel data is completed. As a result, the count value C15 corresponding to the frequency of the gradation value n is stored in the counter register 15 of each processor element PEn. Thereafter, the external data transfer device 2 outputs a process end notification indicating that the last pixel data has been processed to the GP 10. In response to this, the GP 10 outputs a read command to the counter register 15 of each processor element PEn, and in response to this, each counter register 15 outputs the count value C15 to the GP 10 for histogram generation processing. Exit.

  In FIG. 4, the number of executions of the process A1 included in one process B2 varies depending on the distribution of gradation values of the pixel data to be processed. For example, when the distribution of gradation values of the pixel data to be processed is biased, the number of executions of the process A1 included in one process B2 is the maximum value (255) of the count value C12 of the microcounter 12. ) Is relatively close. However, when the distribution of gradation values of the pixel data to be processed is not biased, the number of executions of the process A1 included in one process B2 is larger than the maximum value of the count value C12 of the microcounter 12, Compared to the first embodiment, it is not necessary to interrupt the processing by the data transfer apparatus 2 and execute the parallel addition process PA every time the process A1 is repeated 255 times, and the interrupt interval (that is, the parallel addition process) PA execution interval). As a result, the period during which other processing can be executed by the SIMD type microprocessor 1A becomes longer, and the throughput of the entire system is further improved.

  In the present embodiment, the IRQ condition determination circuit 16 determines whether or not the count value C12 is equal to 255. However, the present invention is not limited to this, and the count value C12 is a predetermined value that is equal to or less than the maximum value of the count value C12. It may be determined whether or not it is equal to the threshold value.

  Further, after reading the count value C15 from each counter register 15, the pixel data to be processed may be added, and the process B2 may be continued.

  Furthermore, in response to the interrupt request signal, the GP 10 controls the external data transfer device 2 so as not to execute the process A2. However, the present invention is not limited to this, and the execution interval of the process A2 is set to the parallel addition process PA. When it is sufficiently longer than the period required for execution, the GP 10 does not need to control the external data transfer apparatus 2 so as not to execute the process A2 in response to the interrupt request signal.

Third embodiment.
FIG. 5 is a block diagram showing a configuration of a SIMD type microprocessor 1B according to the third embodiment of the present invention, and FIG. 6 is a sequence showing a histogram generation process executed by the SIMD type microprocessor 1B of FIG. FIG.

  In FIG. 5, the SIMD type microprocessor 1B includes a GP 10, 256 processor elements PE0B, PE1B,..., PE255B, an IRQ signal line 31 connected to the GP 10, and a DC power source that outputs a predetermined power supply voltage Vcc. A pull-up resistor 32 connected between the IRQ signal line 31 is provided. Each processor element PEnB is assigned a unique address n corresponding to the processor element number n. Here, each processor element PEnB includes a decoder and controller 11A instead of the decoder and controller 11 and a shift register 12A instead of the microcounter 12 compared to the processor element PEnA according to the second embodiment. Instead of the IRQ condition determination circuit 16, an IRQ condition determination circuit 16A is provided.

  In each processor element PEnB of FIG. 5, the decoder and controller 11A inputs an address signal and a control signal from the external data transfer device 2, and the address included in the address signal matches the address n of the processor element PEnB. When the control signal indicates data writing, an instruction signal S11A for instructing upshifting is generated and output to the shift register 12A. In each processor element PEnB, the shift register 12A includes eight 1-bit registers connected in cascade. In response to the instruction signal S11A instructing the upshift, the shift register 12A outputs the most downstream value C12Au of the stored 8-bit bit data C12A to the IRQ condition determination circuit 16A, and each bit of the bit data C12A Data (0 or 1) is shifted to the downstream register by one stage according to the input clock, and 1 is stored in the most upstream register. Each shift register 12A resets the bit data C12A to “00000000” in response to the reset command from the GP 10. Note that the output terminal of the shift register 12A is connected to one input terminal of the ALU 14 via the arithmetic data bus 21.

  In FIG. 5, in each processor element PEnB, the IRQ condition determination circuit 16A controls the nMOSFET 17 to be turned on when the input value C12Au is 1, whereby an interrupt request signal is output to the GP10. The Each IRQ condition determination circuit 16A and nMOSFET 17 of the processor elements PE0B to PE255B, the IRQ signal line 31, and the pull-up resistor 32 are stored in at least one shift register 12A among the shift registers 12A of the processor elements PE0B to PE255B. When the bit data C12A becomes a predetermined threshold bit data (in this embodiment, “11111111”) corresponding to the bit width of the shift register 12A, an interrupt request signal is generated to the GP10. An interrupt request signal generating means for outputting is configured.

  Next, a histogram generation process executed by the SIMD type microprocessor 1B will be described with reference to FIG. First, the GP 10 outputs a reset command to the shift register 12A and the counter register 15 of each processor element PEnB. In response to this, in each processor element PEn, the shift register 12A resets the bit data 12A to “00000000”, and the counter register 15 resets the count value C15 to zero. Next, the GP 10 outputs, to the external data transfer device 2, a process start command that instructs to start process A3 described later. In response to this, the external data transfer device 2 executes the process A3.

  In process A3, when the external data transfer device 2 inputs one pixel data from the external device, the external data transfer device 2 generates an address signal including the gradation value of the input pixel data as an address and a control signal indicating data writing. To the decoder and controller 11 of each processor element PEn. In response to this, the decoder and controller 11 of each processor element PEn determines whether the address included in the input address signal is n and whether the input control signal indicates data writing, and YES In this case, an instruction signal S11A for instructing upshifting is generated and output to the shift register 12A. On the other hand, in the case of NO, the instruction signal S11A is not generated. Further, in response to the instruction signal S11A instructing upshifting, the shift register 12A shifts the bit data C12A by one stage to the downstream register and stores 1 in the most upstream.

  Subsequent to the processing A3, in each processor element PEn, the IRQ condition determination circuit 16A determines whether or not the input value C12Au is 1, and controls to turn on the corresponding nMOSFET 17 if NO. As a result, an interrupt request signal is generated and output to the GP 10. That is, an interrupt request signal is generated when the bit data C12A is “11111111” in at least one processor element PEnB. When the bit data C12A is other than “11111111” in all the processor elements PE0B to PE255B, the process A4 including the process A3 and the determination process by the IRQ condition determination circuit 16A is repeated as shown in FIG. Executed. That is, when the process A3 is repeatedly executed, the value of each bit data C12A changes like “00000000”, “10000000”, “11000000”,. When the bit data C12A of at least one shift register 12A becomes “11111111”, the corresponding IRQ condition determination circuit 16A generates an interrupt request signal and outputs it to the GP10.

  In response to the interrupt request signal, the GP 10 controls the external data transfer apparatus 2 so as not to execute the process A4, and outputs the cumulative addition instruction A1 to the ALUs 14 of all the processor elements PE0B to PE255B. In response to this, the ALU 14 of each processor element PEnB adds 1 to the count value C15 only when the bit data C12A is equal to “10000000”, and outputs the count value C14 of the addition result to the counter register 15. Next, the GP 10 outputs the cumulative addition instruction A2 to the ALUs 14 of all the processor elements PE0B to PE255B. In response to this, the ALU 14 of each processor element PEnB adds 1 to the count value C15 only when the bit data C12A is equal to “11000000”, and outputs the count value C14 of the addition result to the counter register 15. Similarly, the GP 10 sequentially outputs the cumulative addition instructions A3, A4,..., A8 to the ALUs 14 of all the processor elements PE0B to PE255B. Here, the cumulative addition instruction Am (m = 1, 2,..., 8) sets m to the count value C15 only when 1 is stored in the bits from the most upstream to the m-th bit of the bit data C12A. This is an instruction for adding and outputting the count value C14 of the addition result to the counter register 15. Since the addition processing by each ALU 14 of the processor elements PE0B to PE255B is executed by the parallel operation function of the SIMD type microprocessor 1B, it ends in a relatively short time.

  The GP 10 outputs the cumulative addition instruction A8 to all the processor elements PE0B to PE255BALU14, and then outputs a reset instruction to the shift register 12A of each processor element PEnB. In response to this, the bit data C12A of all the shift registers 12A is reset to “00000000”. Further, the GP 10 controls the external data transfer device 2 to execute the process A4.

  In FIG. 6, the process B3 including the process A4, the cumulative addition instructions A1 to A8, and the subsequent reset process of the shift register 12A is repeatedly executed until the process for the last pixel data is completed. As a result, the count value C15 corresponding to the frequency of the gradation value n is stored in the counter register 15 of each processor element PEnB. Thereafter, the external data transfer device 2 outputs a process end notification indicating that the last pixel data has been processed to the GP 10. In response to this, the GP 10 outputs a read command to the counter register 15 of each processor element PEn, and in response to this, each counter register 15 outputs the count value C15 to the GP 10 for histogram generation processing. Exit.

  In FIG. 6, the number of executions of the process A3 included in one process B3 varies depending on the distribution of gradation values of the pixel data to be processed. For example, when the distribution of gradation values of pixel data to be processed is biased, the number of executions of processing A3 included in one processing B3 is the bit width of the shift register 12A (8 in this embodiment). )) Is relatively close. However, when the distribution of the gradation values of the pixel data to be processed is not biased, the number of executions of the process A3 included in one process B3 is larger than the bit width of the shift register 12A.

  In general, since the shift register has a simpler configuration than the counter register, the shift register 12A can be realized with a simpler circuit configuration than the microcounter 12 having a count-up function. Therefore, the circuit scale and power consumption can be reduced as compared with the SIMD type microprocessor 1A according to the second embodiment.

  In addition, after reading the count value C15 from each counter register 15, the pixel data to be processed may be added and the process B3 may be continued.

  Furthermore, in response to the interrupt request signal, the GP 10 controls the external data transfer apparatus 2 so as not to execute the process A4. However, the present invention is not limited to this, and the execution interval of the process A4 is determined by the cumulative addition instructions A1 to A1. When it is sufficiently longer than the period required for executing A8, the GP 10 does not need to control the external data transfer apparatus 2 so as not to execute the process A4 in response to the interrupt request signal.

Fourth embodiment.
FIG. 7 is a block diagram showing a configuration of a SIMD type microprocessor 1C according to the fourth embodiment of the present invention, and FIG. 8 is a sequence showing a histogram generation process executed by the SIMD type microprocessor 1C of FIG. FIG.

  In FIG. 7, the SIMD type microprocessor 1C includes a GP 10, 256 processor elements PE0C, PE1C,..., PE255C, an IRQ signal line 31 connected to the GP 10, and a DC power source that outputs a predetermined power supply voltage Vcc. A pull-up resistor 32 connected between the IRQ signal line 31 is provided. Each processor element PEnC is assigned a unique address n corresponding to the processor element number n. Here, each processor element PEnC further includes an encoder 18 provided between the shift register 12A and the operation data bus 21 as compared with the processor element PEnB according to the third embodiment. . In FIG. 7, the encoder 18 encodes the bit data C12A output from the shift register 12A into binary data C18 and outputs it to the ALU 14 via the arithmetic data bus 21.

  Next, a histogram generation process executed by the SIMD type microprocessor 1C will be described with reference to FIG. The histogram generation process in FIG. 8 differs from the histogram generation process in FIG. 6 only in the process after the timing at which the interrupt request signal is output to the GP 10. In response to the interrupt request signal, the GP 10 controls the external data transfer device 2 so as not to execute the process A4, and reads the binary data C18 output to the arithmetic data bus 21 from the ALU 14 of each processor element PEnC. To control. Next, the parallel addition process PA1 is executed. In the parallel addition process PA1, the GP 10 outputs the cumulative addition instruction A0 to the ALUs 14 of all the processor elements PE0C to PE255C. In response to this, the ALU 14 of each processor element PEnC adds the input binary data C18 and the count value C15, and outputs the count value C14 of the addition result to the counter register 15. Since the addition processing by the ALUs 14 of the processor elements PE0C to PE255C is executed by the parallel operation function of the SIMD type microprocessor 1C, it ends in a relatively short time.

  Next, the GP 10 outputs a reset instruction to the shift register 12A of each processor element PEnC. In response to this, the bit data C12A of all the shift registers 12A is reset to “00000000”. Further, the GP 10 controls the external data transfer device 2 to execute the process A4.

  In FIG. 8, a process B4 including a process A4, a parallel addition process PA1, and a subsequent reset process of the shift register 12A is repeatedly executed until the process for the last pixel data is completed. As a result, the count value C15 corresponding to the frequency of the gradation value n is stored in the counter register 15 of each processor element PEnC. Thereafter, the external data transfer device 2 outputs a process end notification indicating that the last pixel data has been processed to the GP 10. In response to this, the GP 10 outputs a read command to the counter register 15 of each processor element PEn, and in response to this, each counter register 15 outputs the count value C15 to the GP 10 for histogram generation processing. Exit.

  In the third embodiment, since the bit data C12A stored in the shift register 12A is output to the ALU 14, it is necessary to sequentially execute eight cumulative addition instructions A1 to A8 in the process B3. On the other hand, in the present embodiment, the bit data C12A is converted into binary data C18 and output to the ALU 14, so that the cumulative addition process by the ALU 14 need only be executed once in the process B4. Therefore, the number of cumulative additions can be minimized as compared with the third embodiment, and a histogram can be generated at high speed.

  In each of the above embodiments, the histogram generation processing is executed for pixel data of 256 gradations, but the present invention is not limited to this, and can be applied to pixel data of an arbitrary number of gradations. In this case, each of the SIMD type microprocessors 1, 1A, 1B, and 1C includes processor elements PEn, PEnA, PEnB, and PEnC that are equal to or larger than the number of gradations of the pixel data.

  In each of the above embodiments, the micro counter 12, the shift register 12A, and the counter register 15 are reset in response to a reset command from the GP 10, respectively, but the present invention is not limited to this, and the external data transfer device 2 may be controlled so as to write a predetermined initial value.

  Furthermore, in each of the above embodiments, the histogram of the gradation value of the pixel data is generated. However, the present invention is not limited to this, and the histogram of other pixel values such as the density of each color component of the pixel data may be generated. Good.

  As described above, according to the SIMD type microprocessor and the processing method of the SIMD type microprocessor according to the present invention, each processor element of the SIMD type microprocessor has a unique address corresponding to a pixel value, A cumulative addition means having a first bit width and storing means for storing the frequency of the pixel value corresponding to the unique address; and a predetermined second bit width smaller than the first bit width. And counter means for storing a predetermined count value. Each time an address signal is input to the SIMD type microprocessor, the counter means of the processor element having the address included in the input address signal increments the count value by one. Further, the control means adds each of the cumulative addition means so as to cumulatively add the count value stored in the counter means of each processor element to the frequency stored in the storage means corresponding to the counter means at a predetermined timing. The parallel addition processing to be controlled is executed, and the count value stored in the counter means of each processor element is controlled to be reset. Therefore, a histogram can be generated at a higher speed than in the prior art, and the throughput of the entire system can be improved.

  The SIMD type microprocessor and the processing method of the SIMD type microprocessor according to the present invention can be used for apparatuses that execute image processing, such as digital cameras, digital television broadcast receivers, printer apparatuses, and digital copying machines.

1, 1A, 1B, 1C ... SIMD type microprocessor,
2 ... External data transfer device,
10 ... Global processor,
11A: Decoder and controller,
12 ... Micro counter,
12A: Shift register,
13: Cumulative addition circuit,
14 ... ALU,
15: Counter register,
16, 16A ... IRQ condition determination circuit,
17 ... nMOSFET,
18 ... Encoder,
21, 22 ... arithmetic data bus,
31 ... IRQ signal line,
32 ... Pull-up resistor,
PE0-PE255, PE0A-PE255A, PE0B-PE255B, PE0C-PE255C... Processor elements.

JP 2001-84229 A. JP 2002-300407 A.

Claims (12)

In a SIMD (Single Instruction Stream Multiple Data Stream) type microprocessor that sequentially inputs an address signal including pixel values of pixel data as addresses and generates a histogram of each pixel value of a plurality of pixel data,
A plurality of processor elements each having a unique address corresponding to a pixel value, and a storage unit having a predetermined first bit width and storing a frequency of the pixel value corresponding to the unique address A plurality of processor elements each having an adding means and a counter means having a predetermined second bit width smaller than the first bit width and storing a predetermined count value;
Control means for controlling each of the processor elements,
Each time the address signal is input to the SIMD type microprocessor, the counter means of the processor element having the address included in the input address signal increments the count value by 1.
The control means sets the cumulative addition means so as to cumulatively add the count value stored in the counter means of each processor element to the frequency stored in the storage means corresponding to the counter means at a predetermined timing. A SIMD type microprocessor characterized by performing parallel addition processing to be controlled and controlling to reset the count value stored in the counter means of each processor element. When the count value stored in at least one of the counter means of the plurality of processor elements reaches a predetermined threshold count value corresponding to the second bit width, an interrupt request signal is An interrupt request signal generating means for generating and outputting to the control means;
In response to the interrupt request signal, the control means performs the parallel addition process and controls the count value stored in the counter means of each processor element to be reset to zero. The SIMD type microprocessor according to claim 1.   3. The SIMD type microprocessor according to claim 1, wherein the counter means of each processor element is a shift register having a plurality of cascade-connected registers. Each of the processor elements further includes an encoder that encodes the count value stored in the shift register into binary data and outputs the binary data to the cumulative addition unit corresponding to the shift register,
The cumulative addition means of each processor element is characterized in that instead of the count value, binary data input from the encoder corresponding to the cumulative addition means is cumulatively added to the frequency stored in the storage means. The SIMD type microprocessor according to claim 3.   5. The SIMD type microprocessor according to claim 1, wherein the cumulative addition means of each processor element comprises an arithmetic logic operation circuit for the cumulative addition.   6. The SIMD type microprocessor according to claim 1, wherein the pixel value is a gradation value. In a processing method of a SIMD type microprocessor that sequentially inputs an address signal including a pixel value of pixel data as an address and generates a histogram of each pixel value of a plurality of pixel data,
The SIMD type microprocessor is
A plurality of processor elements each having a unique address corresponding to a pixel value, and a storage unit having a predetermined first bit width and storing a frequency of the pixel value corresponding to the unique address A plurality of processor elements each having an adding means and a counter means having a predetermined second bit width smaller than the first bit width and storing a predetermined count value;
Control means for controlling each of the processor elements,
The above processing method is
Each time the address signal is input to the SIMD type microprocessor, a counter means of a processor element having an address included in the input address signal increments the count value by one;
Each of the cumulative addition means is configured to cumulatively add the count value stored in the counter means of each processor element to the frequency stored in the storage means corresponding to the counter means at a predetermined timing. A processing method for the SIMD type microprocessor, comprising: performing parallel addition processing to be controlled, and controlling to reset a count value stored in the counter means of each processor element. In the SIMD type microprocessor, the count value stored in at least one of the counter means of the plurality of processor elements becomes a predetermined threshold count value corresponding to the second bit width. And further comprising an interrupt request signal generating means for generating an interrupt request signal and outputting it to the control means,
In the processing method, in response to the interrupt request signal, the control unit performs the parallel addition processing and controls the count value stored in the counter unit of each processor element to be reset to zero. 8. The processing method of the SIMD type microprocessor according to claim 7, further comprising a step.   9. The SIMD microprocessor processing method according to claim 7, wherein the counter means of each processor element is a shift register having a plurality of cascade-connected registers. Each of the processor elements further includes an encoder that encodes the count value stored in the shift register into binary data and outputs the binary data to the cumulative addition unit corresponding to the shift register,
In the processing method, the cumulative addition means of each processor element cumulatively adds binary data input from the encoder corresponding to the cumulative addition means to the frequency stored in the storage means instead of the count value. 10. The SIMD microprocessor processing method according to claim 9, further comprising a step of:   11. The processing method of the SIMD type microprocessor according to claim 7, wherein the cumulative addition means of each processor element includes an arithmetic logic operation circuit for the cumulative addition. .   12. The processing method of the SIMD type microprocessor according to claim 7, wherein the pixel value is a gradation value.

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