JPH0784761A - Arithmetic processor - Google Patents

Abstract

PURPOSE:To provide an inexpensive arithmetic processor whose hardware amount is remarkably reduced without increasing arithmetic processing time too much. CONSTITUTION:This arithmetic processor is constituted of a multiplier register SR 1 holding a n-bit multiplier and performing 1-bit shift by synchronizing with a clock, a partial product generation part generating the partial product of the shift output of the multiplier register and an m-bit number to be multiplier, an addition part adding the output of the partial product generation part and the output of an intermediate result register and an output register holding an intermediate result register REG 16 and an output of the addition part and the multiplication result of the multiplier and a number to be multiplied. For the period of one cycle of the clock, the generation of the partial product of the shift output of the multiplier register SR 1 and the number to be multiplied, the addition of the output of the partial product generation part and the output of the intermediate result register, the holding of the output of the addition part to the intermediate result register and the writing operation of one of the outputs of the addition part in the most significant bit of the output register are successively performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic unit incorporated in a data processor, a microprocessor or the like,
In particular, the present invention relates to a low-cost arithmetic device that reduces the amount of hardware and suppresses an increase in arithmetic processing time.

[0002]

2. Description of the Related Art In data processors and microprocessors, multiplication is one of the most important operations.
Several calculation methods for multiplication have been proposed according to the required performance and the allowable hardware amount.

FIG. 10 shows a conventional multiplier (first conventional example).
It is a block diagram of. The multiplier of this conventional example is a multiplier that adopts a carry save adder method, and includes 8-bit multiplicand data X (X <0> -X <7>) and 8-bit multiplier data Y (Y <0. > -Y <7>) and outputs the multiplication result OUT (OUT <0> -OUT <15>).

In FIG. 10, the multiplier comprises an 8-bit multiplicand register XR for holding the multiplicand X, an 8-bit multiplier register YR for holding the multiplier Y, and a multiplication unit for performing multiplication.

The multiplication unit is composed of an 8-stage partial product calculation array and a carry look ahead adder CLAADDER connected to the final stage partial product calculation array. The partial product calculation array includes, for each stage, a partial product generator including eight logical product gates that generate partial products, seven full adders FADD and one half adder that cumulatively add partial products. HA
And an adder including a DD. For reference, a truth table of outputs Z and CO for inputs A, B and C of full adder FADD is shown in FIG. 2A, and an output Z for inputs B and C of half adder HADD is shown in FIG. 2B. The truth table of CO is shown respectively.

First, in the first stage partial product calculation array,
The logical product of the outputs X <0> -X <7> of the multiplicand register XR and the output Y <0> of the multiplier register YR is calculated, and the output of the partial product calculation array of the first stage is the partial product of the second stage. Added to the computational array. Next, in the partial product calculation array of the second stage, the output of the partial product calculation array of the first stage, the outputs X <0> -X <7> of the multiplicand register XR, and the output Y <of the multiplier register YR. 1> and are used to perform partial addition of partial products.

Similarly, cumulative addition is sequentially performed by the partial product calculation arrays from the third stage to the eighth stage, and finally the carry look ahead adder CLAADDER outputs the partial product calculation array of the eighth stage. Carry look-ahead addition is performed on the carry look-ahead adder CLAADDER and the multiplication result OUT <0> -OU
As T <8>, the outputs of the half adders HADD located in the least significant bits from the second stage to the eighth stage are respectively generated as multiplication results OUT <9> -OUT <15>, and a multiplication result is generated. .

In such a first conventional multiplier, the number of bits corresponding to the product (64) of the number of bits of the multiplier Y (8 in the example of FIG. 10) and the number of bits (8) of the multiplicand X. A product calculation circuit (AND gate and full adder or half adder) is required. For example, in the case of a multiplier that multiplies 32-bit data, as many as 32 × 32 = 1024 partial product addition circuits are required, which significantly increases the area of the circuit.

Next, FIG. 11 shows a configuration diagram of a multiplication device according to a second conventional example. The conventional multiplication device is a multiplication device using repetitive addition, and has 32-bit data X (X <X
0:31>) and 32-bit data Y (Y <0:31>)
Multiplies by.

In FIG. 11, the multiplier includes a 32-bit multiplicand register XR holding a multiplicand X, a 32-bit multiplier register YR holding a multiplier Y, a 32-bit register ZR holding a cumulative addition result during multiplication, A 32-bit adder ADDER that adds the contents of the multiplicand register XR and the register ZR, and an adder ADDER when the least significant bit Y <31> of the multiplier register YR is "1"
Output ADD <0:31> of the selector ZLR for selecting and outputting the output Z <0:31> of the register ZR when Y <31> is “0”. The final multiplication result is stored in the multiplier register YR.

In the multiplication device of this conventional example, the carry output CARRY of the adder ADDER is written in the most significant bit Z <0> of the register ZR, and at the same time Z <of the register ZR is set.
1:31>, the output SEL <0:30> of the selector SELR
And the most significant bit Z of the multiplier register YR
<0> is the least significant bit SEL <of the output of the selector SELR
31> is written to Y <1:31> of the multiplier register YR and Y <0:30> of the multiplier register YR is repeated 32 times.

That is, as one processing unit, the multiplier Y
Depending on the value Y <i> (i = 0 to 31) of each digit of the multiplicand X <0:31
＞ is added by shifting 1 bit to the right (Y <i> =
1) or a process of right-shifting the contents of the register ZR by 1 bit without adding (when Y <i> = 0) and the multiplication result determined in the i-th process The th bit to the most significant bit of the multiplier register YR,
A process of storing the multiplier register YR while shifting it to the right by one bit is performed. This processing unit is performed 32 times (i = 0
~ 31) As a result of repeated execution, the lower 32 bits of the multiplication result are in the multiplier register YR and the upper 32 bits are in the register Z.
It will be stored in R respectively.

In such a second conventional multiplication device,
It is necessary to repeat the above-mentioned processing unit the number of times of the number of bits of the multiplier (32 times), and the addition of the adder ADDER requires a long operation time because of carry propagation, resulting in a very long operation time of multiplication. Become.

[0014]

As described above, in the conventional arithmetic unit for performing multiplication, the hardware amount becomes very large when a high-speed multiplier is constructed as in the first conventional example. However, there is a trade-off problem that the calculation time becomes very long when trying to reduce the amount of hardware as in the second conventional example.

The present invention solves the above-mentioned problems.
An object of the present invention is to provide a low-cost arithmetic device in which the amount of hardware is greatly reduced without increasing the arithmetic processing time.

[0016]

FIG. 1 is a diagram for explaining the principle of the present invention.

In order to solve the above problems, the first aspect of the present invention
1 has a n-bit (n is an arbitrary positive integer; n = 8 in FIG. 1) multiplier SR <0: 7> as shown in FIG.
Multiplier register SR for shifting one bit in the direction from the most significant bit MSB to the least significant bit LSB in synchronization with the clock
1 and the shift output of the multiplier register SR1 and m bits (m is an arbitrary positive integer; m = 8 in FIG. 1) multiplicand A <
0: 7> for generating a partial product, an adder for adding the output of the partial product and an output of an intermediate result register described later, and an intermediate result register REG16 for holding the output of the adder. The multiplier SR <0: 7> and the multiplicand A
An output register that holds a multiplication result OUT <0: 7> of <0: 7>, and a shift output SR <7> of the multiplier register SR1 and a multiplicand A <0: in a period of one cycle of the clock. 7>, a partial product is generated, addition of the output of the partial product and the output of the intermediate result register REG16, holding of the output of the adder in the intermediate result register REG16, and one of the outputs of the adder are stored in the output register. The operation of writing to the most significant bit MSB and shifting the output register by 1 bit from the most significant bit to the least significant bit,
It should be done sequentially.

The second feature of the present invention is, as shown in FIG. 3, n bits (n is an arbitrary positive integer; n = 8 in FIG. 3).
A multiplier that holds the multiplier SR <0: 7> of p and shifts p bits (p is a positive integer less than or equal to n; p = 2 in FIG. 3) in the direction from the most significant bit MSB to the least significant bit LSB in synchronization with the clock. A partial product of the register SR2 and the shift output 1 bit SR <7> of the multiplier register SR2 and the m-bit (m is any positive integer; m = 8 in FIG. 3) multiplicand A <0: 7> is generated. Partial product generator of the first stage, output of the partial product generator of the first stage, and intermediate result register output REG1 described later.
6 in the first stage, and the i-th stage for generating a partial product of the i-th bit (i = 2 to p) from the most significant bit of the multiplier register SR2 and the multiplicand. A partial product generation unit, an i-th stage addition unit that adds the i-th stage partial product generation unit output and the i-1th stage partial product generation unit output, and the p-th stage addition An intermediate result register REG16 for holding a partial output and an output register for holding a multiplication result of the multiplier SR <0: 7> and the multiplicand A <0: 7>. Generation of a partial product of the shift output 1 bit of the multiplier register SR2 and the multiplicand, addition of the partial product generation unit output of the first stage and the intermediate result register REG16 output, and the second to p-th stages Operation of partial product generator and adder, adder of p-th stage Holding the force in the intermediate result register REG16 and writing p bits of the output of the adder of the least significant digit of the 1st to pth stages from the most significant bit of the output register to the most significant bit of the output register. The operation of shifting p bits in the direction of the least significant bit is sequentially performed.

A third feature of the present invention is that, in the arithmetic unit according to claim 1 or 2, as shown in FIG. 1 or 3, the multiplier register SR1 or SR2 and the output register also serve as a dual-purpose register SR1. Alternatively, it is realized by SR2.

Further, a fourth feature of the present invention is as follows.
In the arithmetic unit described in 2 or 3, as shown in FIG. 4, the arithmetic unit uses the clock generation circuit CLKGEN for generating the clock CLOCK and the clock based on an arithmetic start signal START given from the outside of the arithmetic unit. A predetermined number of clocks C from the generation circuit CLKGEN
And a control circuit CNT for generating LOCK.

The fifth feature of the present invention is that in the arithmetic unit according to the fourth aspect, the clock generation circuit CLK.
GEN includes a part of the multiplier register SR1, a part of the adder, and a part of the partial product generator, or a part of the multiplier register SR2, an adder from the first stage to the p-th stage, and This is to have the same configuration as part of the partial product generators from the first stage to the p-th stage.

Further, a sixth feature of the present invention is that the control circuit CNT is a signal indicating that the arithmetic unit is in execution of arithmetic operation from the receipt of the arithmetic start signal START to the end of the arithmetic operation. It is to output READY to the outside.

[0023]

In the arithmetic units having the first and third features of the present invention,
As shown in FIG. 1, the partial product generation unit generates a partial product of the shift output SR <7> of the multiplier register SR1 and the multiplicand A <0: 7> during the period of one cycle of the clock CLOCK, and the addition unit generates a partial product. The output of the product generator and the output of the intermediate result register REG16 are added, the output of the adder is held in the intermediate result register REG16, and one of the outputs of the adder (sum output Z of the least significant digit) is stored in the output register. A series of operations of writing to the upper bit MSB and shifting the output register by 1 bit from the most significant bit to the least significant bit is sequentially performed. In the arithmetic unit of the third feature, since it is realized by the register SR1 which also serves as the multiplier register and the output register, the shift operation is performed only once at the beginning.

As described above, the multiplication array is realized by a carry-save type partial product calculation array (partial product generation unit and addition unit) having a minimum number of stages, and the time required for one cycle is reduced by repeating the above cycle. It is possible to realize a low-cost arithmetic device with a shortened circuit scale and a greatly reduced circuit scale.

Further, in the arithmetic units having the second and third characteristics of the present invention, as shown in FIG. 3, the shift output 1 bit SR <7> of the multiplier register SR2 and the multiplicand A are provided in the period of one cycle of the clock CLOCK. First the partial product with <0: 7>
It is generated by the partial product generation unit of the first stage, and the output of the partial product generation unit of the first stage and the intermediate result register R by the addition unit of the first stage.
The output of the EG16 is added, the operations of the partial product generation unit and the addition unit from the second stage to the pth stage are sequentially performed, and the output of the addition unit of the pth stage is held in the intermediate result register REG16. To p bits of the output of the adder of the least significant digit in the p-th stage are written from the most significant bit of the output register to the p bits, and the output register is shifted from the most significant bit to the least significant bit in the direction of p.
A series of operations such as bit shifting are sequentially performed. In the arithmetic unit of the third feature, since it is realized by the register SR2 which also serves as the multiplier register and the output register, the shift operation is performed only once at the beginning.

As described above, the multiplication array is realized by the p-stage carry-save type partial product calculation array (p-stage partial product generation section and addition section), and the number of bits of the multiplicand is repeated in p repetition cycles. Perform multiplication. In other words, the number of stages p of the partial product calculation array can be set according to the required arithmetic processing speed and the amount of hardware, and a trade-off between the arithmetic processing speed and the amount of hardware can be realized, and as a result, the time required for one cycle can be reduced. At the same time, it is possible to realize a low-cost arithmetic device in which the circuit scale is reduced without significantly increasing the overall arithmetic processing time.

Further, in the arithmetic units of the fourth, fifth, and sixth features of the present invention, as shown in FIG. 4, the control circuit CNT controls the clock based on the arithmetic start signal START given from the outside of the arithmetic unit. The generation circuit CLKGEN is controlled to generate a predetermined number of clocks CLOCK.

Generally, a processor including a multiplication circuit or connected to the multiplication circuit needs an oscillator for generating a high-speed clock for the multiplication circuit in or around the processor, but the oscillator cost is high and the oscillator is high. There is a problem in that the delay time from the power supply circuit to the multiplication circuit is large, and the power consumption is increased due to the routing of the clock signal line. By providing the clock generation circuit CLKGEN in the arithmetic unit (multiplication circuit), the above problems are overcome,
High-speed arithmetic processing can be realized.

In particular, in the arithmetic unit having the fifth characteristic of the present invention, as shown in FIG. 5, the clock generating circuit CLKGEN has a configuration in which a part or part of the multiplier register SR1 is provided for the multiplying unit having the first characteristic. Part of the multiplier register SR2, the first stage to the p-th stage have the same configuration as the product generation unit and a part of the addition unit (configured with devices of the same size), and for the arithmetic unit of the second feature. The multiplication array and the clock generation circuit CLKG have the same configuration as the addition unit up to the stage and the partial product generation unit from the first stage to the p-th stage.
EN can be given the same delay characteristic, and stable arithmetic operation can be guaranteed without causing a malfunction even under the conditions of the manufacturing process and changes in the surrounding environment.

Further, in the arithmetic unit having the sixth characteristic of the present invention, the control circuit CNT indicates that the arithmetic unit is executing an arithmetic operation from the receipt of the arithmetic start signal START to the completion of the arithmetic operation. The signal READY is output to the outside.

In the processor incorporating the arithmetic unit or the processor connected to the multiplying unit, the processor and the arithmetic unit can be synchronized because they operate at a clock different from the operation clock inside the arithmetic unit. Will be needed. By realizing the synchronization between the processor and the arithmetic unit by the arithmetic start signal START and the signal READY indicating that the arithmetic operation is being executed, it becomes possible to realize without using complicated hardware.

[0032]

Embodiments of the present invention will now be described with reference to the drawings.

(First Embodiment) FIG. 1 shows a block diagram of an arithmetic unit according to a first embodiment of the present invention. The arithmetic unit according to the present embodiment is a carry-save-adder type multiplier that uses a one-stage partial product calculation array, and has 8-bit multiplicand data A (A <0: 7>) and 8-bit multiplicand data. Multiply the multiplier data SR (SR <0: 7>) to obtain the lower 8 bits OUT (OUT <0: 7>) of the multiplication result.

In FIG. 1, the multiplier comprises an 8-bit shift register and holds a multiplier register SR1 for holding a multiplier SR, a cumulative adder for cumulatively adding partial products, and an intermediate result from the cumulative adder. 16-bit intermediate result register REG16. The multiplication result OUT is stored in the multiplier register SR1.

The cumulative addition unit is composed of a one-stage partial product calculation array. The partial product calculation array cumulatively adds partial products with a partial product generation unit composed of eight AND gates AN2 for generating partial products. The number of full adders FADD and one half adder HADD. For reference, the inputs A, B, C of the full adder FADD are shown in FIG.
2B shows a truth table of outputs Z and CO for FIG. 2B, and a truth table of outputs Z and CO for inputs B and C of the half adder HADD.

Next, the operation of the multiplier of this embodiment will be described.

First, the multiplier is written in the multiplier register SR1. Although not shown in FIG. 1, the multiplier register SR1 has 8-bit multiplier data SR <0> -SR <7>.
Is also stored in each bit at the same time. Here, SR <0> is the most significant bit and SR <7> is the least significant bit. In addition, the intermediate result register REG16 is set to "
Clear to 0 ".

Next, the multiplier register SR1 is set to the clock C.
MSB most significant bit in synchronization with LOCK (not shown)
1 bit is shifted in the direction from to the least significant bit LSB.

Next, the partial product generation unit causes the multiplier register S
Partial products of the shift output SR <7> of R1 and the multiplicand A <0: 7> are respectively generated, and the adder adds the partial product generator output and the intermediate result register REG16 output. Here, the j-th bit (j = 2 to 7) full adder FA
DD inputs the output of the partial product generation unit A, and REG <(j−1) × of the intermediate register REG16 held in the previous cycle.
2> is input B, the intermediate register R held in the previous cycle
The REG <(j−1) × 2 + 1> of the EG 16 is used as the input C for full addition to generate a carry output CO and a sum output Z. The eighth adder HADD has the REG of the intermediate register REG16 held in the previous cycle.
Half-addition is performed using <14> as the input B and REG <15> of the intermediate register REG16 held in the previous cycle as the input C to generate the carry output CO and the sum output Z.

Next, the output of the adder is set to the intermediate result register RE.
Hold to G16. The highest-order REG <0> of the intermediate register REG16 holds the result of the logical product of the highest-order bit A <0> of the multiplicand and the shift output SR <7> of the multiplier register SR1, and REG <1>. -REG <14>
Holds the carry output CO and the sum output Z of the full adder FADD, and the REG <15> has a half adder HA.
The carry output CO of DD is held.

Further, the least-significant half-adder HAD of the adder unit
The sum output Z of D is written in the most significant bit MSB of the output register (SR1).

By sequentially repeating the above series of operations eight times, the lower 8 bits of the multiplication result are obtained in the output register SR1 as OUT <0> -OUT <7>.

As described above, in the multiplier of this embodiment, the multiplication array is realized by the carry save type partial product calculation array (partial product generation unit and addition unit) having the minimum number of stages, and the above cycle is repeated. As a result, it is possible to realize a low-cost multiplier in which the time required for one cycle is shortened and the circuit scale is greatly reduced.

(Second Embodiment) FIG. 3 shows a block diagram of an arithmetic unit according to a second embodiment of the present invention. Similar to the first embodiment, the arithmetic unit of the present embodiment is also a multiplier that employs the carry save adder method and uses a two-stage partial product calculation array, and has 8-bit multiplicand data A (A <A < 0: 7>) and 8-bit multiplier data SR (SR <0> -SR <7>)
And the lower 8 bits OUT (OU
T <0> -OUT <7>) is obtained.

In FIG. 3, the multiplier holds a multiplier register SR2 holding a multiplier SR, a cumulative adder for cumulatively adding partial products, and an intermediate result from the cumulative adder 1
It is composed of a 6-bit intermediate result register REG16. The multiplication result OUT is stored in the multiplier register SR2.

The multiplier register SR2 is an 8-bit shift register, but in order to perform a 2-bit shift operation in one cycle, the shift output of SR <0> is changed to SR <2>.
, The shift output of SR <1> to SR <3>, ...

The cumulative addition unit is a two-stage partial product calculation array ST.
It consists of AGE1 and STAGE2. Each partial product calculation array has eight AND gates A for generating partial products.
Partial product generator consisting of N2 and cumulative addition of partial products 7
The number of full adders FADD and one half adder HADD.

Next, the operation of the multiplier of this embodiment will be described.

First, the multiplier is written in the multiplier register SR1. Although not shown in FIG. 3, the multiplier register SR1 has 8-bit multiplier data SR <0> -SR <7>.
Is also stored in each bit at the same time. Here, SR <0> is the most significant bit and SR <7> is the least significant bit. In addition, the intermediate result register REG16 is set to "
Clear to 0 ".

Next, the multiplier register SR1 is set to the clock C.
MSB most significant bit in synchronization with LOCK (not shown)
From the least significant bit to the least significant bit LSB.

Next, the partial product generator of the first stage shifts the shift output SR <7> of the multiplier register SR1 and the multiplicand A <.
0: 7> and the partial product generator output of the first stage and the intermediate result register REG16 output are added by the adder of the first stage. Here, the full adder FADD of the jth bit (j = 2 to 7) inputs the output of the partial product generation unit A, and the intermediate register R held in the previous cycle.
REG <(j-1) × 2> of EG16 is input B, REG <of intermediate register REG16 held in the previous cycle
(J-1) × 2 + 1> is used as the input C for full addition,
Generate carry output CO and sum output Z. Also, the eighth
The half adder HADD of the bit is input B to REG <14> of the intermediate register REG16 held in the previous cycle,
RE of the intermediate register REG16 held in the previous cycle
Half-adding with G <15> as input C is performed to generate carry output CO and sum output Z.

Next, the partial product generator of the second stage generates partial products of SR <6> of the multiplier register SR1 and the multiplicand A <0: 7>, respectively, and the adder of the second stage generates the partial products. Two
The output of the partial product generator of the first stage and the output of the adder of the first stage are added.

Here, the full adder FADD of the jth bit (j = 2 to 7) receives the output of the partial product generating section of the second stage as input A, and the j-1th bit of the adding section of the first stage. Full adder FA
The sum output Z of DD is input B, and the carry output CO of the j-th bit full adder FADD of the first stage adder is used as input C to perform full addition to generate a carry output CO and a sum output Z. However, the B input of the full adder FADD of the second bit is the output of the first bit of the partial product generator of the first stage.

Also, the 8th bit half adder HADD
Is the 7th bit full adder FADD of the adder of the first stage
The input B is used as the sum output Z and the carry output CO of the eighth-bit half adder HADD of the adder of the first stage is used as the input C to perform half addition to generate the carry output CO and the sum output Z.

Next, the output of the adder of the second stage is held in the intermediate result register REG16. The intermediate register REG
The 16 most significant REG <0> holds the result of the logical product of the most significant bit A <0> of the multiplicand and SR <6> of the multiplier register SR1, and REG <1> -REG <14>.
Holds the carry output CO and the sum output Z of the full adder FADD, and the REG <15> has a half adder HA.
The carry output CO of DD is held.

Further, the sum output Z of the half adder HADD of the least significant digit of the adder of the first stage is transferred from the most significant bit MSB of the output register (SR1) to the second bit (SR <1>).
In addition, the half-adder HADD of the least significant digit of the adder in the second stage
The sum output Z is written to the most significant bit MSB (SR <0>) of the output register (SR1).

By sequentially repeating the above series of operations four times, the lower 8 bits of the multiplication result are obtained as OUT <0> -OUT <7> in the output register SR1.

In the multiplier of the first embodiment, the multiplication time is
{(Delay time of partial product calculation array) + (delay time of intermediate result register REG16)} × (number of bits of multiplicand m)
Therefore, there is a drawback that the calculation time of multiplication is long.

On the other hand, in the multiplier of this embodiment, the multiplication array is realized by (p =) two-stage carry-save type partial product calculation array (two-stage partial product generation unit and addition unit). (Number of bits of multiplicand) / (Number of stages of partial product calculation array: 2 stages) = Multiplication can be executed in four repeating cycles. That is, by setting the number p of stages of the partial product calculation array according to the required arithmetic processing speed and the required amount of hardware, a trade-off between the arithmetic processing speed and the required amount of hardware can be realized.

As a result, it is possible to realize a low-cost arithmetic unit in which the time required for one cycle is shortened and the circuit scale is reduced without significantly increasing the overall arithmetic processing time.

(Third Embodiment) FIG. 4 is a block diagram of an arithmetic unit according to the third embodiment of the present invention.

In the figure, the arithmetic unit of this embodiment multiplies the multiplicand data A and the multiplier data B, and the multiplication result O
A multiplier MUL that obtains UT, an internal clock generation circuit CLKGEN that generates an internal clock CLOCK, and a clock control signal SW that is issued based on an operation start signal START given from the outside of the operation device, and a predetermined number is output from the internal clock generation circuit CLKGEN. Internal clock CLOCK
And a control circuit CNT which outputs a multiplication end signal READY indicating that the arithmetic unit is in the middle of arithmetic operation from the reception of the arithmetic start signal START to the end of the arithmetic operation. There is.

The multiplier MUL is the multiplier MUL1 shown in the first embodiment or the multiplier M shown in the second embodiment.
It is UL2.

FIG. 5 shows a circuit diagram of the internal clock generator CLKGEN when the number of stages of MUL1 → MUL2 is two. The internal clock generator CLKGEN in the figure has a configuration when supplied to the multiplier MUL1 (first embodiment), and has a delay time equivalent to the delay time from the multiplier register SR1 to the partial product generation in the multiplier MUL1. And a clock control signal S from the control circuit CNT.
AND gate AN that takes the logical product of W and the output of the dummy circuit
2Y and clock buffers CB1 and CB2.

The dummy circuit is 1 in the multiplier MUL1.
This circuit realizes a circuit having the same delay time as the time required for the multiplication data to pass in one clock cycle, and is configured by a circuit equivalent to one bit of the multiplier register SR1 (elements of the same size are The dummy register SRX (used), a dummy gate AN2X composed of a circuit equivalent to the AND gate AN2, and a dummy full adder FADDX composed of a circuit equivalent to the full adder FADD are provided. .

The control circuit CNT has a clock control signal SW.
When the internal clock CLOCK is generated by a predetermined number, the clock control signal SW is made inactive. That is, in FIG. 5, the clock control signal S
When W is at "H" level, dummy circuit to AND gate A
The internal clock C in which the path of N2Y is turned on and the pulse width is the delay time of the dummy circuit and the AND gate AN2Y
When LOCK is generated and the clock control signal SW is at "L" level, the internal clock CLOCK is stopped.

Generally, a processor equipped with an arithmetic unit or connected to the arithmetic unit needs an oscillator for generating a high-speed clock for the arithmetic unit in or around the processor. There is a problem that the cost of the oscillator (clock generator) is high, the delay time from the oscillator to the arithmetic unit is long, the power consumption increases due to the routing of the clock signal line, and so on. By providing the internal clock generation circuit CLKGEN inside the arithmetic unit as in this embodiment,
The above problems can be overcome and high-speed arithmetic processing can be realized.

Further, there is a problem that the multiplier MUL does not operate when the delay time of the multiplication array is later than the clock cycle generated inside the multiplier. On the other hand, the delay time of the circuit changes depending on the conditions of the manufacturing process, ambient conditions such as voltage and temperature, and the magnitude of the change depends on the type of circuit.

Therefore, the internal clock generation circuit CLKGE
When N is formed by a circuit configuration that is completely different from that of the multiplication array, it is necessary to configure the clock period to be larger than the delay time of the multiplication array even if the conditions change. I need to make it slow enough.

However, as in the present embodiment, the internal clock generation circuit CLKGEN is configured so that, for the arithmetic unit MUL2 of the second embodiment, a part of the multiplier register SR2 and a partial product of the first stage are generated. Section, a part of the first-stage addition section, the multiplication array and the clock generation circuit CLKGEN can have the same delay characteristics, so that even if the manufacturing process conditions and the surrounding environment change, , Stable operation can be guaranteed without causing malfunction.

Further, in the processor incorporating the arithmetic unit or the processor connected to the arithmetic unit, the operating clock of the processor operates at a clock different from the operating clock inside the arithmetic unit.
It is necessary to synchronize the processor and the arithmetic unit.

In this embodiment, the synchronization between the processor and the arithmetic unit is realized by the arithmetic start signal START and the multiplication end signal READY indicating that the arithmetic operation is being executed. That is, by stopping the operation of the processor while the multiplication end signal READY indicates that the arithmetic unit is executing, it is possible to achieve synchronization without using complicated hardware.

(Fourth Embodiment) FIG. 6 shows a block diagram of an arithmetic unit according to a fourth embodiment of the present invention. The arithmetic unit of the present embodiment is a multiplier that employs a carry save adder method and uses a two-stage partial product calculation array, and has 32-bit multiplicand data A (A <0:31>) and 32-bit multiplicand data. Multiplying the multiplier data B (B <0> -B <31>) of 6
4-bit multiplication result OUT (OUT <0> -OUT <6
3>) is obtained.

In the figure, the arithmetic unit of this embodiment has a multiplier register BR for holding a multiplier B, a cumulative adder for cumulatively adding partial products, and a 64-bit for holding an intermediate result from the cumulative adder. An intermediate result register REG64, a final adder FSA that adds the sum and carry for each bit at the end of the operation to calculate a final result, and an internal clock generation circuit CLKGE that generates an internal clock CLOCK.
N and a calculation start signal S given from the outside of the calculation device
The clock control signal SW is generated based on TART to generate a predetermined number of internal clocks CLOCK from the internal clock generation circuit CLKGEN, and the calculation start signal START is generated.
The multiplication end signal READY indicating that the operation device is executing the operation from the reception of the
Is output to the outside. The multiplication result OUT is the output OU of the final addition unit FSA.
T <0:31> and the output OUT <3 of the multiplier register BR
3:63>.

Multiplier register SR2 starts with multiplier B <
0:31>, and then the internal clock CLOCK
Is a 32-bit shift register that performs a 2-bit shift operation in synchronization with the input selector BIS,
An output selector BOS is provided on the output side.

The intermediate result register REG64 is a sum of partial products output from the cumulative addition unit and a carry (intermediate result).
Is a 64-bit register for temporarily holding the input selector RIS on the input side and the output selector ROS on the output side.

The cumulative addition unit is a two-stage partial product calculation array ST.
It consists of AGE1 and STAGE2. Each partial product calculation array includes a partial product generation unit that includes 32 AND gates AN2 that generate partial products, 31 full adders FADD and 1 half adder HADD that cumulatively add partial products.
And an adding section. FIG. 7 shows a detailed circuit configuration diagram of the second stage partial product calculation array.

The internal clock generation circuit CLKGEN is for generating the internal clock CLOCK based on the clock control signal SW and is similar to the internal clock generation circuit CLKGEN (see FIG. 5) in the third embodiment, but this embodiment is the same. The internal clock generation circuit CLKGEN of FIG. 2 has a configuration for the multiplier MUL2 described in the third embodiment, that is, a dummy circuit is a part of the multiplier register SR2, a first-stage partial product generation unit, and a first-stage addition unit. Of the second stage, the partial product generating section of the second stage, and the adding section of the second stage.

The control circuit CNT uses the internal clock CLOC.
Incrementer CINC that counts the number of times K, counter register CTR, incrementer CINC and a
Select the ll-zero value to register the counter CTR
CTS and control signals CTENB and E supplied to
Decoder DEC for generating NB, exclusive OR gate X
O1, OR gate OR1, delay element (delay) DL
Y, clocked inverters CI1 and CI2, and an inverter I3.

FIG. 8 is a timing chart for explaining the operation of the arithmetic unit of this embodiment.

First, each signal shown in the figure and the internal signal used in FIG. 6 will be described.

The calculation start signal START is a signal given from the outside of the calculation device and indicates the start of calculation at the rising edge and the rising edge. The multiplication end signal READY is a signal indicating that the arithmetic unit is executing an arithmetic operation, and notifies that the arithmetic operation is completed at the rising and falling edges. Therefore, as shown in the timing chart of FIG.
When TART ≠ READY and the operation is waiting, ST
ART = READY.

The counter output CT <0: 4> is the output 5 bits of the counter register CTR for temporarily storing the result of the incrementer CINC, and is "0" to "1".
It is incremented up to 6 "in synchronization with the internal clock CLOCK. It is stopped at" 16 "in the operation waiting state, and becomes" 0 "when the initialization of multiplication is performed.

The reset signal CTENB is a signal for first correctly resetting the value of the counter output CT <0: 4>, and CT <0: 4> = by the decoder DEC.
When 10,000, CTENB = 0, CT <0: 4> ≠ 1
When it is 0000, it is generated so that CTENB = 1.
Therefore, during normal operation, CTENB = 1 during multiplication and CTENB = 0 during standby.

The clock control signal SW is the internal clock C.
This is a signal for controlling the generation / stop of LOCK, and SW = 1
When SW = 0, the internal clock CLOCK is generated, and when SW = 0, the internal clock CLOCK is stopped. Clock control signal S
W is a calculation start signal START and a multiplication end signal REA
Exclusive OR of DY (use ^ as symbolic expression)
And the reset signal CTENB. Therefore, SW = 1 while CTENB = 1, and STA when CTENB ≠ 1.
When RT ^ READY = 1, that is, START ≠ READ
When Y (during calculation), SW = 1 and internal clock CLO
When CK is generated and START ^ READY = 0, S
W = 0 and the internal clock CLOCK is stopped.

The internal clock CLOCK is used to control the operation and is generated based on the clock control signal SW. That is, it occurs when SW = 1 and stops when SW = 0 and CL
It is fixed at OCK = 0.

The enable signal ENB is the counter output C.
When T <4> is used, ENB = 1 when the counter indicates "16", and ENB ≠ 1 at other times. Further, the enable signal ENB is an enable signal for initialization, and when ENB = 1, the internal clock CLOC is used.
When K rises, an initialization operation for starting multiplication is performed. When initialization is performed, CT <0: 4> = 0 ≠ 16
Therefore, ENB = 0 is changed. After that, ENB = 0 and ENB = 1 does not hold until the multiplication is completed. Further, since the final addition unit FSA operates while ENB = 1, the addition result will be obtained when the multiplication is completed.

Output of multiplier register BR SHF <0:31
>; When the multiplication is initialized, the multiplier B is loaded with the multiplier B <0:31> as data. During the subsequent calculation, 2 in synchronization with the internal clock CLOCK.
The bits are shifted bit by bit, and the lower bits of the output SHF, SHF <31> and SHF <30>, are output to the partial product generators PSG1 and PSG2, respectively. At the falling edge of the internal clock CLOCK, the least significant bits SO and SO2 are received from the adders SA1 and SA2, respectively, and SH
It is stored as F <0> and SHF <1>. At the end of the multiplication, SHF <0:31> contains the lower 32 bits of the multiplication result.
The bits are held and when ENB = 1 these values are output as part of the result. ENB =
When 0, the lower 32 bits of the result (OUT <33:63
>) Are all fixed to "0".

The sum output S <0:31> of the adder SA2 is
It corresponds to the sum of the outputs from the full adder FADD and the half adder HADD of the adder SA2.

Carry output of adder SA2 C <0:31
> Is a full adder FADD and a half adder HA of the adder SA2
Corresponds to carry in the output from DD.

Output REG of the intermediate result register REG64
<0:63>; the intermediate result register REG64 has S excluding the partial sum SO2 of the least significant bit of the output of the adder SA2.
<0:31> and C <0:31> are temporarily stored.

Next, the operation of the arithmetic unit of this embodiment will be described. Two-stage partial product calculation arrays STAGE1 and STAG
Since the cumulative addition is performed by E2, the processing by the two-stage partial product calculation arrays STAGE1 and STAGE2 is performed 16 times.
The multiplication is executed by repeating each time.

(A) At the time of reset When the power is turned on, it is necessary to perform a reset operation and set a value so that a correct calculation is performed. This reset operation is automatically performed as needed using the reset signal CTENB. This operation will be described below.

It is the value held in the counter register CTR that needs to be reset to set the correct value. Normally, the register CTR
Holds the value CT <0: 4> = 100 when waiting for calculation
00, CT <0: 4><10000 during calculation. Therefore, when the calculation is not performed, the value of the counter is "100.
It must be "00".

If CT <0: 4) ≠ 10000, CTENB = 1 and SW = (START ^ RE
Since ADY) | CTENB = 1, the internal clock CLOCK is forcibly generated regardless of other signals.
The symbol "|" indicates a logical sum.

Since the internal clock CLOCK is generated in this way, the incrementer CINC operates and counts up. When CT <0: 4> = 10000, CTENB = 0, SW = 0, and the internal clock CLOCK is stopped (at this time, START = R
EADY). Therefore, the counter is also stopped with CT <0: 4> = 10000. At this time, the final addition unit FSA
, The result is output, but of course, the output result has no meaning.

As described above, the reset operation of the operation is completed, and the operation waits for the instruction to start the multiplication.

(B) At the time of operation The start of multiplication is notified by the rise of the multiplication start signal START, as shown in the timing chart of FIG. Since START = READY when waiting for an operation and CTENB = 0 due to the above reset operation, SW = (START ^ READY) | CTENB
= 0. When the calculation start signal START rises, START ≠ READY, SW = 1, and the internal clock CLOCK is generated.

At this time, since ENB = CT <0> = 1, the operation of initializing the multiplier occurs at the same time when the internal clock CLOCK rises. In this embodiment, this initialization operation is performed by the internal clock CLO when ENB = 1.
It shall occur when CK rises. Therefore,
When ENB = 0, initialization does not occur even if the internal clock CLOCK rises.

(B-1) Initialization Operation First, CT <0: 4> = from the counter register CTR.
00000 is output. Therefore, CT <0> ≠ 1, that is, ENB = CT <0> = 0. This means that initialization can occur only once in one multiplication.

When the multiplier register BR is initialized, the lower bits B <31> and B <30> are output to the partial product generators PSG1 and PSG2 via SHF <31> and SHF <30>. Supplied. Further, in the intermediate result register REG64, "0" is output from all bits at the time of initialization.

In response to the above output, the partial product generator PSG
1, PSG2, and the addition units SA1 and SA2 operate to generate sums S <0:31> and SO2 for each bit and carry C <0:31>.

The above initialization operation is performed by the parallel multiplier (first
This is the same as the completion of the second stage out of the 32 stages in the conventional example).

(B-2) Other Operations Next, operations at the falling edge of the clock will be described.

First, with respect to the counter register CTR, an increment operation is performed and a value counted up by one is stored.

Regarding the multiplier register BR, the value shifted to the right by 2 bits is held as SHF <2:31>. At this time, the upper 2 bits of the multiplier register BR SHF <
In 0: 1>, the least significant bits SO and SO2 of the sum are fetched from the adders SA1 and SA2, respectively.

Regarding the intermediate result register REG64,
Sum S <0:31 output from adder SA2 in the second stage
> And carry C <0:31> are stored as intermediate results.

Next, the operation at the rising edge of the internal clock CLOCK will be described.

From the counter register CTR to CT <0:
4> is supplied to the incrementer CINC. From the multiplier register BR, the lower 2 bits SHF <31> and SHF <30> of SHF <0:31> are supplied to the partial product generators PSG1 and PSG2, respectively. In addition, REG <0:63> is output from the intermediate result register REG64.
Is supplied to the addition unit SA1 of the first stage.

Upon receipt of the above inputs, the partial product generator PSG
1, PSG2 and addition units SA1 and SA2 operate.
Since this operation is equivalent to performing the operation for two stages of the parallel multipliers, if this operation is repeated 16 times, 32 bits of partial products are generated and they are cumulatively added.

Therefore, when CT <0: 4> = 10000 is output from the register CTR serving as a counter, that is, when the counter indicates "16", ENB =
CT <0> = 1. When ENB = 1, the multiplication end signal READY rises to inform the outside of the multiplication. Since the multiplication end signal READY has risen, READY = START, and at this time C
Since TENB = 0, SW = 0. Therefore, the internal clock CLOCK is stopped.

At the same time, since ENB = 1, the final adder FSA operates and the carry C <0:31> of the second-stage adder SA2 and the partial sum S <0:31> of each bit.
Perform the operation to add. As a result, the result of OUT <0:32> for the upper 33 bits of the multiplication result is obtained. Further, when ENB = 1, part of the multiplication result held in the multiplier register BR can be taken out. These are the lower 31 bits of the multiplication result OUT <3
3:63>.

That is, from the above, the output OUT <0:63> = {final adder FSA output 33
Bit, SHF <0:31>}.

After the multiplication result is obtained, CT <0: 4>
= 10000, ENB = 1, CTENB = 0 are maintained, multiplier register BR, intermediate result register REG64
The value of is also retained. At the same time, since the final addition unit FSA continues to output, the multiplication result is held until the next multiplication starts.

After that, when the multiplier B and the multiplicand A change and the multiplication start signal START rises next, the next multiplication is started and the above operation is repeated and the multiplication result is output.

FIG. 9 is an overall configuration diagram of a data processing device to which the arithmetic unit of the fourth embodiment is applied.

The data processing device is a microprocessor M.
It is composed of a PU and an external memory EXTMEM.

The microprocessor unit MPU takes in the arithmetic unit EXU for performing arithmetic operations on data, the bus interface unit BIU for controlling the interface with the external memory EXTMEM, and the external clock EXTCLK to take in the multiplication end signal READY from the multiplication device MPY.
A clock buffer CBUF that generates an internal clock CLOCK based on the bus interface unit BIU
It is composed of an instruction decode unit IDU which decodes the instruction INST fetched via the and generates a control signal inside the microprocessor MPU.

The arithmetic unit EXU comprises an arithmetic unit (multiplier) MPY, an arithmetic logic unit ALU, and a general-purpose register GR.

As described above, in the processor MPU including the arithmetic unit MPU, the operating clock CLK of the processor MPU operates at a clock different from the operating clock CLOCK inside the arithmetic unit MPU. It is necessary to synchronize between MPYs.

In the present embodiment, the synchronization between the processor MPU and the arithmetic unit MPY is realized by the arithmetic start signal START and the multiplication end signal READY indicating that the arithmetic operation is being executed.

That is, while the multiplication end signal READY indicates that the arithmetic unit MPY is executing,
An arithmetic logic operation unit ALU in the operation unit EXU,
In addition, by stopping the operation of other units in the processor MPU, that is, the bus interface unit BIU and the instruction decode unit IDU, the control is simplified and synchronization is achieved without using complicated hardware such as a PLL circuit. It becomes possible.

[0123]

As described above, according to the present invention,
By implementing the multiplication array with a carry-save partial product calculation array (partial product generation unit and addition unit) with a minimum number of stages, and repeating the processing in the partial product calculation array,
While reducing the processing time in the partial product calculation array,
It is possible to provide a low-cost arithmetic device with a greatly reduced circuit scale.

According to the present invention, the multiplication array is realized by a p-stage carry save type partial product calculation array (p-stage partial product generation section and addition section) (bit number of multiplicand) /
Since the multiplication is executed in p repetition cycles, the number of stages p of the partial product calculation array is set according to the required arithmetic processing speed and the amount of hardware to realize the trade-off between the arithmetic processing speed and the amount of hardware. And as a result,
It is possible to provide a low-cost arithmetic device in which the time required for one cycle is shortened, the overall arithmetic processing time is not significantly increased, and the circuit scale is reduced.

Further, according to the present invention, the control circuit generates the predetermined number of clocks from the clock generation circuit based on the calculation start signal given from the outside of the arithmetic unit, so that a high-speed clock dedicated to the periphery is generated. It is possible to provide low-cost, high-speed arithmetic processing without requiring a generation unit.

In particular, by making the configuration of the clock generation circuit the same as that of the multiplier register, the partial product generation unit, and the addition unit (configured by devices of the same size), the same delay is applied to the multiplication array and the clock generation circuit. The characteristics can be provided, and stable arithmetic operation can be guaranteed without causing a malfunction even under the conditions of the manufacturing process and changes in the surrounding environment.

Further, from the control circuit, the signal indicating that the arithmetic operation is being executed is output to the outside from the time when the arithmetic start signal is received until the arithmetic operation is completed. It is possible to realize the synchronization with the processor having the built-in processor or the processor connected to the multiplication device without using complicated hardware.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an arithmetic unit according to a first embodiment of the present invention.

FIG. 2 (a) shows inputs A, B, of a full adder FADD.
A truth table of outputs Z and CO for C, and FIG. 2B is a truth table of outputs Z and CO for inputs B and C of the half adder HADD.

FIG. 3 is a configuration diagram of an arithmetic unit according to a second embodiment of the present invention.

FIG. 4 is a configuration diagram of an arithmetic unit according to a third embodiment of the present invention.

FIG. 5 is a circuit configuration diagram of a clock generator in a third embodiment.

FIG. 6 is a configuration diagram of an arithmetic unit according to a fourth embodiment of the present invention.

FIG. 7 is a detailed circuit configuration diagram of a second stage partial product calculation array in the fourth embodiment.

FIG. 8 is a timing chart illustrating the operation of the arithmetic unit according to the fourth embodiment.

FIG. 9 is an overall configuration diagram of a data processing device to which an arithmetic device according to a fourth embodiment is applied.

FIG. 10 is a configuration diagram of a conventional multiplier (first conventional example).

FIG. 11 is a configuration diagram of a multiplication device according to a second conventional example.

[Explanation of symbols]

A (A <0: 7>) Multiplicand data B (B <0: 7>) Multiplier data SR (SR <0> -SR <7>) Multiplier data OUT (OUT <0> -OUT <7>) Multiplication result Lower 8 bits of SR1 multiplier register REG16 intermediate result register AN2 AND gate FADD full adder HADD half adder SR2 multiplier register STAGE1 first stage partial product calculation array STAGE2 second stage partial product calculation array MUL multiplier MUL1 Multiplier MUL2 shown in the first embodiment Multiplier shown in the second embodiment CLKGEN Internal clock generation circuit CNT control circuit SW Clock control signal AN2Y AND gate CB1, CB2 Clock buffer SRX dummy register AN2X dummy gate FADDX Dummy full adder A (A <0:31>) Multiplicand Data B (B <0:31>) Multiplier data OUT (OUT <0:63>) Multiplication result BR Multiplier register REG64 Intermediate result register FSA Final adder BIS Multiplier register input selector BOS Multiplier register output selector RIS Intermediate result Register input selector ROS Intermediate result register output selector PSG1, PSG2 Partial product generator SA1, SA2 adder FSA final adder S '<0:31>, C'<0:31> Partial product calculation of the first stage Array result S <0:31>, C <0:31> Second stage partial product calculation Array result REG <0:63> Output of intermediate result register SHF <0:31> Output of multiplier register CNT control Circuit CLKGEN Internal clock generation circuit START Multiplication start signal READY Multiplication end signal CLOCK Internal clock CINC incrementer STS counter input selector CTR counter register DEC decoder CT <0: 4> counter output ENB enable signal CTENB reset signal XO1 exclusive OR gate OR1 logical OR gate DLY delay CI1, CI2 clocked inverter I1 inverter MPU Microprocessor EXTMEM External memory EXU Operation unit BIU Bus interface unit CBUF Clock buffer IDU Instruction decode unit MPY Operation unit (multiplier) ALU Arithmetic and logic operation unit GR General register BUS Internal bus EXTCLK External clock INST instruction X (X <0> -X <7>) Multiplicand data Y (Y <0> -Y <7>) Multiplier data OUT (OUT <0> -OUT <15 >) Multiplication result XR Multiplicand register YR Multiplier register CLAADDER Carry look ahead adder X (X <0:31>) Multiplicand data Y (Y <0:31>) Multiplier data ZR Register holding cumulative addition result during multiplication Z <0:31> Output of register ZR ADDER 32-bit adder ADD <0:31> Output of adder ADDER SELR selector SEL <0:31> Output of selector SELR

Claims (6)

[Claims] 1. A multiplier register that holds a multiplier of n bits (n is any positive integer) and shifts by 1 bit in the direction from the most significant bit to the least significant bit in synchronization with a clock; and a shift output of the multiplier register. And a partial product generation unit that generates a partial product of an m-bit (m is an arbitrary positive integer) multiplicand, an addition unit that adds the partial product generation unit output and an intermediate result register output described below, and the addition unit output And an output register for holding a multiplication result of the multiplier and the multiplicand, generating a partial product of the shift output of the multiplier register and the multiplicand during the period of one cycle of the clock, Addition of the output of the partial product and the output of the intermediate result register, holding the output of the adder in the intermediate result register, and writing one of the outputs of the adder to the most significant bit of the output register An arithmetic unit characterized by sequentially performing an operation of shifting the output register by 1 bit from the most significant bit to the least significant bit. 2. A multiplier that holds a multiplier of n bits (n is any positive integer) and shifts by p bits (p is a positive integer of n or less) in the direction from the most significant bit to the least significant bit in synchronization with a clock. Register, and the shift output of the multiplier register, 1 bit and m bits (m
Is an arbitrary positive integer) and a first-stage partial product generator for generating a partial product with a multiplicand, and a first stage for adding an output of the partial product generator of the first stage and an output of an intermediate result register described later. And an i-th bit from the least significant bit of the multiplier register (i =
2 to p) bit and the multiplicand, the i-th stage partial product generation unit, the i-th stage partial product generation unit output, and the i-1th stage partial product generation unit An i-th stage adder for adding an output, an intermediate result register for holding an output of the p-th stage adder, and an output register for holding a multiplication result of the multiplier and the multiplicand, the clock In the period of one cycle of, the generation of the partial product of the shift output 1 bit of the multiplier register and the multiplicand, the addition of the partial product generation unit output of the first stage and the intermediate result register output, the second stage Calculation of the partial product generation unit and the addition unit up to the p-th stage, holding of the output of the addition unit of the p-th stage in the intermediate result register, and p of the addition unit output of the lowest digit of the 1st to p-th stages Write the bit portion from the most significant bit of the output register to p bits, The force register from the most significant bit operation to p bit shifted to the least significant bit direction, the arithmetic apparatus characterized by sequentially performed. 3. The arithmetic unit according to claim 1, wherein the multiplier register and the output register are realized by dual-purpose registers. 4. The arithmetic unit includes a clock generating circuit for generating the clock, and a control circuit for generating a predetermined number of clocks from the clock generating circuit based on an arithmetic start signal given from the outside of the arithmetic unit. The arithmetic unit according to claim 1, 2 or 3, characterized by comprising. 5. The clock generation circuit includes a part of the multiplier register, a part of the adder unit, and a part of the partial product generator, or a part of the multiplier register, the first to pth stages. The arithmetic unit according to claim 4, which has the same configuration as a part of the adding unit up to the eye and a part of the partial product generating unit from the first stage to the p-th stage. 6. The control circuit outputs, to the outside, a signal indicating that the operation device is executing an operation from when the operation start signal is received to when the operation is completed. The arithmetic unit according to Item 4 or 5.